SNAS736C June   2017  – April 2019 LMX2595

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Reference Path
        1. 7.3.2.1 OSCin Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Programmable Multiplier (MULT)
        4. 7.3.2.4 Post-R Divider (PLL_R)
        5. 7.3.2.5 State Machine Clock
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N-Divider and Fractional Circuitry
      5. 7.3.5  MUXout Pin
        1. 7.3.5.1 Lock Detect
        2. 7.3.5.2 Readback
      6. 7.3.6  VCO (Voltage-Controlled Oscillator)
        1. 7.3.6.1 VCO Calibration
        2. 7.3.6.2 Determining the VCO Gain
      7. 7.3.7  Channel Divider
      8. 7.3.8  VCO Doubler
      9. 7.3.9  Output Buffer
      10. 7.3.10 Power-Down Modes
      11. 7.3.11 Phase Synchronization
        1. 7.3.11.1 General Concept
        2. 7.3.11.2 Categories of Applications for SYNC
        3. 7.3.11.3 Procedure for Using SYNC
        4. 7.3.11.4 SYNC Input Pin
      12. 7.3.12 Phase Adjust
      13. 7.3.13 Fine Adjustments for Phase Adjust and Phase SYNC
      14. 7.3.14 Ramping Function
        1. 7.3.14.1 Manual Pin Ramping
          1. 7.3.14.1.1 Manual Pin Ramping Example
        2. 7.3.14.2 Automatic Ramping
          1. 7.3.14.2.1 Automatic Ramping Example (Triangle Wave)
      15. 7.3.15 SYSREF
        1. 7.3.15.1 Programmable Fields
        2. 7.3.15.2 Input and Output Pin Formats
          1. 7.3.15.2.1 Input Format for SYNC and SysRefReq Pins
          2. 7.3.15.2.2 SYSREF Output Format
        3. 7.3.15.3 Examples
        4. 7.3.15.4 SYSREF Procedure
      16. 7.3.16 SysRefReq Pin
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power-Up Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
      3. 7.5.3 General Programming Requirements
    6. 7.6 Register Maps
      1. 7.6.1  General Registers R0, R1, & R7
        1. Table 25. Field Descriptions
      2. 7.6.2  Input Path Registers
        1. Table 26. Field Descriptions
      3. 7.6.3  Charge Pump Registers (R13, R14)
        1. Table 27. Field Descriptions
      4. 7.6.4  VCO Calibration Registers
        1. Table 28. Field Descriptions
      5. 7.6.5  N Divider, MASH, and Output Registers
        1. Table 29. Field Descriptions
      6. 7.6.6  SYNC and SysRefReq Input Pin Register
        1. Table 30. Field Descriptions
      7. 7.6.7  Lock Detect Registers
        1. Table 31. Field Descriptions
      8. 7.6.8  MASH_RESET
        1. Table 32. Field Descriptions
      9. 7.6.9  SysREF Registers
        1. Table 33. Field Descriptions
      10. 7.6.10 CHANNEL Divider And VCO Doubler Registers
        1. Table 34. Field Descriptions
      11. 7.6.11 Ramping and Calibration Fields
        1. Table 35. Field Descriptions
      12. 7.6.12 Ramping Registers
        1. 7.6.12.1 Ramp Limits
          1. Table 36. Field Descriptions
        2. 7.6.12.2 Ramping Triggers, Burst Mode, and RAMP0_RST
          1. Table 37. Field Descriptions
        3. 7.6.12.3 Ramping Configuration
          1. Table 38. Field Descriptions
      13. 7.6.13 Readback Registers
        1. Table 39. Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
      5. 8.1.5 Performance Comparison Between 1572 (0x0624) and 3115 (0x0C2B) for Register DBLR_IBIAS_CTRL1 (R25[15:0])
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

(3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ +85°C, except as specified. Nominal values are at VCC = 3.3 V, TA = 25°C)
MIN NOM MAX UNIT
SYNC, SYSRefReq, RampClk, and RampDIR Pins
tSETUP Setup time for pin relative to OSCin rising edge SYNC pin 2.5 ns
SysRefReq pin 2.5
tHOLD Hold time for SYNC pin relative to OSCin rising edge SYNC pin 2 ns
SysRefReq pin 2
DIGITAL INTERFACE WRITE SPECIFICATIONS
fSPIWrite SPI write speed tCWL + tCWH > 13.333 ns 75 MHz
tCE Clock to enable low time See Figure 1 5 ns
tDCS Data to clock setup time 2 ns
tCDH Clock to data hold time 2 ns
tCWH Clock pulse width high 5 ns
tCWL Clock pulse width low 5 ns
tECS Enable to clock setup time 5 ns
tEWH Enable pulse width high 2 ns
DIGITAL INTERFACE READBACK SPECIFICATIONS
fSPIReadback SPI readback speed See Figure 2 50 MHz
tCE Clock to enable low time 10 ns
tDCS Data to clock setup time 2 ns
tCDH Clock to data hold time 2 ns
tCR Clock falling edge to available readback data wait time. 0 10 ns
tCWH Clock pulse width high 10 ns
tCWL Clock pulse width low 10 ns
tECS Enable to clock setup time 10 ns
tEWH Enable pulse width high 10 ns
LMX2595 timing-01-SNAS696.gifFigure 1. Serial Data Input Timing Diagram

There are several other considerations for writing on the SPI:

  • The R/W bit must be set to 0.
  • The data on SDI pin is clocked into a shift register on each rising edge on the SCK pin.
  • The CSB must be held low for data to be clocked. Device will ignore clock pulses if CSB is held high.
  • When SCK and SDI lines are shared between devices, TI recommends to hold the CSB line high on the device that is not to be clocked.
  • Note that tCE is only a valid spec if CPOL (Clock Polarity) = 0 and CPHA (Clock Phase) = 0 is used for SPI protocol. For SPI mode (CPOL = 1 and CPHA = 1), the minimum distance required between the last rising edge of clock and the rising edge of CSB is tCE + clock_period/2.

LMX2595 timing-02-SNAS696.gifFigure 2. Serial Data Readback Timing Diagram

There are several other considerations for SPI readback:

  • The R/W bit must be set to 1.
  • The MUXout pin will always be low for the address portion of the transaction.
  • The data on MUXout is clocked out at tCR after the falling edge of SCK. In other words, the readback data will be available at the MUXout pin tCR after the clock falling edge.
  • The data portion of the transition on the SDI line is always ignored.