SNAS739 Data sheet

SNAS739D June 2018 – May 2020 LMX2615-SP

PRODUCTION DATA.

(3.2 V ≤ V_CC ≤ 3.45 V, –55°C ≤ T_A ≤ +125°C, except as specified. Nominal values are at V_CC = 3.3 V, T_A = 25°C)

			MIN	MAX	UNIT
DIGITAL INTERFACE WRITE SPECIFICATIONS
f_SPIWrite	SPI write speed			2	MHz
t_CE	Clock to enable low time	See Figure 1	50		ns
t_CS	Data to clock setup time		50		ns
t_CH	Data to clock hold time		50		ns
t_CWH	Clock pulse width high		200		ns
t_CWL	Clock pulse width low		200		ns
t_CES	Enable to clock setup time		100		ns
t_EWH	Enable pulse width high		100		ns
DIGITAL INTERFACE READBACK SPECIFICATIONS
f_SPIReadback	SPI readback speed			2	MHz
t_CE	Clock to enable low time	See Figure 2	50		ns
t_CS	Clock to data wait time		50		ns
t_CWH	Clock pulse width high		200		ns
t_CWL	Clock pulse width low		200		ns
t_CES	Enable to clock setup time		50		ns
t_EWH	Enable pulse width high		100		ns
t_CD	Falling clock edge to data wait time		200		ns

Figure 1. Serial Data Input Timing Diagram

There are several other considerations for writing on the SPI:

The R/W bit must be set to 0.
The data on SDI pin is clocked into a shift register on each rising edge on the SCK pin.
The CSB must be held low for data to be clocked. Device will ignore clock pulses if CSB is held high.
The CSB transition from high to low must occur when SCK is low.
When SCK and SDI lines are shared between devices, TI recommends hold the CSB line high on the device that is not to be clocked.

Figure 2. Serial Data Readback Timing Diagram

There are several other considerations for SPI readback:

The R/W bit must be set to 1.
The MUXout pin will always be low for the address portion of the transaction.
The data on MUXout becomes available momentarily after the falling edge of SCK and therefore should be read back on the rising edge of SCK.
The data portion of the transition on the SDI line is always ignored.