7.6.2 R1 Register (Address = 0x1) [reset = 0x3]
R1 is shown in Figure 53 and described in Table 10.
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Figure 53. R1 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
CAL_CLK_DIV |
R-0x0 |
R/W-0x3 |
|
Table 10. R1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-3 |
RESERVED |
R |
0x0 |
|
2-0 |
CAL_CLK_DIV |
R/W |
0x3 |
Divides down for state machine clock [SM clock = Fosc/2CAL_CLK_DIV]. Maximum state machine clock frequency is 200MHz. For fastest calibration speed, choose value which will make state machine clock closest to 200 MHz. |