7.6.26 R81 Register (Address = 0x51) [reset = 0x0]
R81 is shown in Figure 77 and described in Table 34.
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Figure 77. R81 Register
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
RESERVED |
LO_POLY_MODE1 |
R-0x0 |
R/W-0x0 |
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
EXTLO_CLK_DIV_EN |
LO_DRVR_MODE |
RESERVED |
EXTLO_CLK_DRV_EN |
SM_CLK_SEL |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 34. R81 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15-12 |
RESERVED |
R |
0x0 |
|
11-8 |
LO_POLY_MODE1 |
R/W |
0x0 |
Sets up parameters for the poly path
0x0 = Internal LO Poly
0x15 = External LO
0x19 = Internal LO DIV2
|
7-6 |
EXTLO_CLK_DIV_EN |
R/W |
0x0 |
Selects driver for SMCLK
0x0 = Internal LO
0x1 = Reserved
0x2 = Reserved
0x3 = External LO
|
5-4 |
LO_DRVR_MODE |
R/W |
0x0 |
Sets up drivers for LO quadrature path
0x0 = Internal LO Poly
0x1 = Internal LO DIV2
0x2 = Reserved
0x3 = External LO
|
3 |
RESERVED |
R |
0x0 |
|
2-1 |
EXTLO_CLK_DRV_EN |
R/W |
0x0 |
Enables drivers for state machine clock. |
0 |
SM_CLK_SEL |
R/W |
0x0 |
Selects the state machine clock source for the signal path
0x0 = Internal LO
0x1 = External LO
|