SNVS723H October   2011  – October 2023 LMZ10500

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Start-up Behavior and Soft Start
      3. 7.3.3 Output Short Circuit Protection
      4. 7.3.4 Thermal Overload Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Circuit Operation
      2. 7.4.2 Input Undervoltage Detection
      3. 7.4.3 Shutdown Mode
      4. 7.4.4 EN Pin Operation
      5. 7.4.5 Internal Synchronous Rectification
      6. 7.4.6 High Duty Cycle Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
          1. 8.2.2.2.1 RT and RB Selection for Fixed VOUT
          2. 8.2.2.2.2 Output Voltage Accuracy Optimization
        3. 8.2.2.3 Dynamic Output Voltage Scaling
        4. 8.2.2.4 Integrated Inductor
        5. 8.2.2.5 Input and Output Capacitor Selection
      3. 8.2.3 Application Curves
        1. 8.2.3.1 VOUT = 1.2 V
        2. 8.2.3.2 VOUT = 1.8 V
        3. 8.2.3.3 VOUT = 2.5 V
        4. 8.2.3.4 VOUT = 3.3 V
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Voltage Range
      2. 8.3.2 Current Capability
      3. 8.3.3 Input Connection
        1. 8.3.3.1 Voltage Drops
        2. 8.3.3.2 Stability
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Package Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • SIL|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 Layout Guidelines

The board layout of any DC/DC switching converter is critical for the optimal performance of the design. Bad PCB layout design can disrupt the operation of an otherwise good schematic design. Even if the regulator still converts the voltage properly, the board layout can mean the difference between passing or failing EMI regulations. In a Buck converter, the most critical board layout path is between the input capacitor ground terminal and the synchronous rectifier ground. The loop formed by the input capacitor and the power FETs is a path for the high di/dt switching current during each switching period. This loop must always be kept as short as possible when laying out a board for any Buck converter.

The LMZ10500 integrates the inductor and simplifies the DC/DC converter board layout. Refer to the example layout in Figure 8-26. There are a few basic requirements to achieve a good LMZ10500 layout.

  1. Place the input capacitor CIN as close as possible to the VIN and PGND pins. VIN (pin 7) and PGND (pin 6) on the LMZ10500 are next to each other which makes the input capacitor placement simple.
  2. Place the VCON filter capacitor CVC and the RB RT resistive divider as close as possible to the VCON and SGND terminals.The CVC capacitor (not RB) must be the component closer to the VCON pin, as shown in Figure 8-26. This allows for better bypass of the control voltage set at VCON.
  3. Run the feedback trace (from VOUT to FB) away from noise sources.
  4. Connect SGND to a quiet GND plane.
  5. Provide enough PCB area for proper heatsinking. Refer to the Section 6.5 table for example θJA values for different board areas. Also, refer to AN-2020 for additional thermal design hints.

Refer to the evaluation board user's guide LMZ10501SIL and LMZ10500SIL SIMPLE SWITCHER® Nano Module Evaluation Board for a complete board layout example.