SNVS723H October   2011  – October 2023 LMZ10500

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Start-up Behavior and Soft Start
      3. 7.3.3 Output Short Circuit Protection
      4. 7.3.4 Thermal Overload Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Circuit Operation
      2. 7.4.2 Input Undervoltage Detection
      3. 7.4.3 Shutdown Mode
      4. 7.4.4 EN Pin Operation
      5. 7.4.5 Internal Synchronous Rectification
      6. 7.4.6 High Duty Cycle Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
          1. 8.2.2.2.1 RT and RB Selection for Fixed VOUT
          2. 8.2.2.2.2 Output Voltage Accuracy Optimization
        3. 8.2.2.3 Dynamic Output Voltage Scaling
        4. 8.2.2.4 Integrated Inductor
        5. 8.2.2.5 Input and Output Capacitor Selection
      3. 8.2.3 Application Curves
        1. 8.2.3.1 VOUT = 1.2 V
        2. 8.2.3.2 VOUT = 1.8 V
        3. 8.2.3.3 VOUT = 2.5 V
        4. 8.2.3.4 VOUT = 3.3 V
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Voltage Range
      2. 8.3.2 Current Capability
      3. 8.3.3 Input Connection
        1. 8.3.3.1 Voltage Drops
        2. 8.3.3.2 Stability
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Package Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • SIL|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-2C78646A-2EBF-4AB1-8C61-63B26DCC81C9-low.gifFigure 5-1 SIL Package,8-Pin µSIP
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 EN I Enable input. Set this digital input higher than 1.2 V for normal operation. For shutdown, set low. Pin is internally pulled up to VIN and can be left floating for always-on operation.
2 VCON I Output voltage control pin. Connect to analog voltage from resisitve divider or DAC/controller to set the VOUT voltage. VOUT = 2.5 × VCON. Connect a small (470 pF) capacitor from this pin to SGND to provide noise filtering.
3 FB I Feedback of the error amplifier. Connect directly to output capacitor to sense VOUT.
4 SGND I Ground for analog and control circuitry. Connect to PGND at a single point.
5 VOUT O Output Voltage. Connected to one pin of the integrated inductor. Connect output filter capacitor between VOUT and PGND.
6 PGND I Power ground for the power MOSFETs and gate-drive circuitry.
7 VIN I Voltage supply input. Connect ceramic capacitor between VIN and PGND as close as possible to these two pins. Typical capacitor values are between 4.7 µF and 22 µF.
8 VREF O 2.35 V voltage reference output. Typically connected to VCON pin through a resistive divider to set the output voltage.
— PAD I The center pad underneath the SIL0008A package is internally tied to SGND. Connect this pad to the ground plane for improved thermal performance.
(1) I = input, O = output