SNVS633K January   2010  – April 2019 LMZ10505

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
      2.      Efficiency VOUT = 3.3 V
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Enable and UVLO
      3. 7.3.3 Soft-Start
      4. 7.3.4 Soft-Start Capacitor
      5. 7.3.5 Tracking
      6. 7.3.6 Tracking - Equal Soft-Start Time
      7. 7.3.7 Tracking - Equal Slew Rates
      8. 7.3.8 Current Limit
      9. 7.3.9 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Prebias Start-Up Capability
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Input Capacitor Selection
        3. 8.2.2.3 Output Capacitor Selection
          1. 8.2.2.3.1 Output Voltage Setting
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Application Schematic for 3.3-V to 5-V Input and 2.5-V Output With Optimized Ripple and Transient Response
      2. 8.3.2 Application Schematic for 3.3-V to 5-V Input and 2.5-V Output
      3. 8.3.3 EMI Tested Schematic for 2.5-V Output Based on 3.3-V to 5-V Input
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Estimate Power Dissipation and Thermal Considerations
    4. 10.4 Power Module SMT Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.4 Loop Compensation

The LMZ10505 preserves flexibility by integrating the control components around the internal error amplifier while utilizing three small external compensation components from VOUT to FB. An integrated type II (two pole, one zero) voltage-mode compensation network is featured. To ensure stability, an external resistor and small value capacitor can be added across the upper feedback resistor as a pole-zero pair to complete a type III (three pole, two zero) compensation network. The compensation components recommended in Table 4 provide type III compensation at an optimal control loop performance. The typical phase margin is 45° with a bandwidth of 80 kHz. Calculated output capacitance values not listed in Table 4 should be verified before designing into production. The AN-2013 LMZ1050x/LMZ1050xEXT SIMPLE SWITCHER Power Module (SNVA417) is a detailed application note that provides verification support. In general, calculated output capacitance values below the suggested value will have reduced phase margin and higher control loop bandwidth. Output capacitance values above the suggested values will experience a lower bandwidth and increased phase margin. Higher bandwidth is associated with faster system response to sudden changes such as load transients. Phase margin changes the characteristics of the response. Lower phase margin is associated with underdamped ringing and higher phase margin is associated with overdamped response. Losing all phase margin will cause the system to be unstable; an optimized area of operation is 30° to 60° of phase margin, with a bandwidth of 100 kHz ±20 kHz.

LMZ10505 30107408.pngFigure 22. Loop Compensation Control Components

Table 4. LMZ10505 Compensation Component Values

VIN (V) CO (µF) ESR (mΩ) Rfbt (kΩ)(1) Ccomp (pF)(1) Rcomp (kΩ)(1)
MIN MAX
5 22 2 20 200 27 1.5
47 2 20 124 68 1.4
100 1 10 82.5 150 0.681
150 1 5 63.4 220 1
150 10 25 63.4 220 3.48
150 26 50 226 62 12.1
220 15 30 150 100 6.98
220 31 60 316 560 14
3.3 22 2 20 118 43 9.09
47 2 20 76.8 100 3.32
100 1 10 49.9 180 2.49
150 1 5 40.2 330 1
150 10 25 43.2 330 4.99
150 26 50 143 100 7.5
220 15 30 100 180 4.99
220 31 60 200 100 8.06
(1) In the special case where the output voltage is 0.8 V, TI recommends to remove Rfbb and keep Rfbt, Rcomp, and Ccomp for a type III compensation.