SNVS649I January   2010  – October 2015 LMZ14201

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 COT Control Circuit Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Overvoltage Comparator
      2. 7.3.2 Current Limit
      3. 7.3.3 Thermal Protection
      4. 7.3.4 Zero Coil Current Detection
      5. 7.3.5 Prebiased Start-Up
    4. 7.4 Device Functional Modes
      1. 7.4.1 Discontinuous Conduction and Continuous Conduction Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Design Steps for the LMZ14201 Application
          1. 8.2.2.1.1 Enable Divider, RENT and RENB Selection
          2. 8.2.2.1.2 Output Voltage Selection
          3. 8.2.2.1.3 Soft-Start Capacitor Selection
          4. 8.2.2.1.4 CO Selection
          5. 8.2.2.1.5 CIN Selection
          6. 8.2.2.1.6 RON Resistor Selection
            1. 8.2.2.1.6.1 Discontinuous Conduction and Continuous Conduction Mode Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Module SMT Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation and Board Thermal Requirements
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
VIN, RON to GND –0.3 43.5 V
EN, FB, SS to GND –0.3 7 V
Junction Temperature 150 °C
Storage Temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
(3) For soldering specifications, see product folder at www.ti.com and SNOA549.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN 6 42 V
EN 0 6.5 V
Operation Junction Temperature −40 125 °C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

6.4 Thermal Information

THERMAL METRIC(1) LMZ14201 UNIT
NDW (TO-PMOD)
7 PINS
RθJA Junction-to-ambient thermal resistance 4 layer JEDEC Printed Circuit Board, 100 vias, No air flow 19.3 °C/W
2 layer JEDEC Printed Circuit Board, No air flow 21.5
RθJC(top) Junction-to-case (top) thermal resistance 1.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Limits are for TJ = 25°C only unless otherwise noted. Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 24 V, Vout = 3.3 V
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
SYSTEM PARAMETERS
ENABLE CONTROL(3)
VEN EN threshold trip point VEN rising 1.18 V
over the junction temperature (TJ) range of –40°C to +125°C 1.10 1.25
VEN-HYS EN threshold hysteresis VEN falling 90 mV
SOFT-START
ISS SS source current VSS = 0 V 8 µA
over the junction temperature (TJ) range of –40°C to +125°C 5 11
ISS-DIS SS discharge current -200 µA
CURRENT LIMIT
ICL Current limit threshold DC average 1.95 A
over the junction temperature (TJ) range of –40°C to +125°C 1.4 3
ON/OFF TIMER
tON-MIN ON timer minimum pulse width 150 ns
tOFF OFF timer pulse width 260 ns
REGULATION AND OVERVOLTAGE COMPARATOR
VFB In-regulation feedback voltage VSS >+ 0.8 V
TJ = -40°C to 125°C
IO = 1 A		 0.798 V
over the junction temperature (TJ) range of –40°C to +125°C .777 0.818
VSS > +0.8 V
TJ = 25°C
IO = 10 mA		 0.786 0.802 0.818 V
VFB-OV Feedback overvoltage protection threshold 0.92 V
IFB Feedback input bias current 5 nA
IQ Non Switching Input Current VFB= 0.86 V 1 mA
ISD Shut Down Quiescent Current VEN= 0 V 25 μA
THERMAL CHARACTERISTICS
TSD Thermal Shutdown Rising 165 °C
TSD-HYST Thermal shutdown hysteresis Falling 15 °C
PERFORMANCE PARAMETERS
ΔVO Output Voltage Ripple 8 mV PP
ΔVO/ΔVIN Line Regulation VIN = 12 V to 42 V, IO= 1 A .01%
ΔVO/IOUT Load Regulation VIN = 24 V 1.5 mV/A
η Efficiency VIN = 24 V VO = 3.3 V IO = 1 A 92%
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
(3) EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2024 and layout for information on device under test.

6.6 Typical Characteristics

Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10 uF X7R Ceramic; CO = 100 uF X7R Ceramic; TA = 25 C for efficiency curves and waveforms.
LMZ14201 30114631.gif
Figure 1. Efficiency 6-V Input at 25°C
LMZ14201 30114603.gif
Figure 3. Efficiency 12-V Input at 25°C
LMZ14201 30114626.gif
Figure 5. Efficiency 24-V Input at 25°C
LMZ14201 30114629.gif
Figure 7. Efficiency 36-V Input at 25°C
LMZ14201 30114650.gif
Figure 9. Efficiency 42-V Input at 25°C
LMZ14201 30114633.gif
Figure 11. Efficiency 6-V Input at 85°C
LMZ14201 30114640.gif
Figure 13. Efficiency 8-V Input at 85°C
LMZ14201 30114642.gif
Figure 15. Efficiency 12-V Input at 85°C
LMZ14201 30114644.gif
Figure 17. Efficiency 24-V Input at 85°C
LMZ14201 30114646.gif
Figure 19. Efficiency 36-V Input at 85°C
LMZ14201 30114652.gif
Figure 21. Efficiency 42-V Input at 85°C
LMZ14201 30114648.gif
Figure 23. Line and Load Regulation at 25°C
LMZ14201 30114605.gif
Figure 25. Output Ripple
24VIN 3.3 VO 1 A, BW = 200 MHz
LMZ14201 30114670.gif
Figure 27. Thermal Derating VOUT = 3.3 V
LMZ14201 30114654.gif
Figure 29. Current Limit 3.3 VOUT at 25°C
LMZ14201 30114632.gif
Figure 2. Dissipation 6-V Input at 25°C
LMZ14201 30114604.gif
Figure 4. Dissipation 12-V Input at 25°C
LMZ14201 30114627.gif
Figure 6. Dissipation 24-V Input at 25°C
LMZ14201 30114630.gif
Figure 8. Dissipation 36-V Input at 25°C
LMZ14201 30114651.gif
Figure 10. Dissipation 42-V Input at 25°C
LMZ14201 30114634.gif
Figure 12. Dissipation 6-V Input at 85°C
LMZ14201 30114641.gif
Figure 14. Dissipation 8-V Input at 85°C
LMZ14201 30114643.gif
Figure 16. Dissipation 12-V Input at 85°C
LMZ14201 30114645.gif
Figure 18. Dissipation 24-V Input at 85°C
LMZ14201 30114647.gif
Figure 20. Dissipation 36-V Input at 85°C
LMZ14201 30114653.gif
Figure 22. Dissipation 42-V Input at 85°C
LMZ14201 30114669.gif
Figure 24. Line and Load Regulation at 85°C
LMZ14201 30114606.gif
Figure 26. Transient Response
24VIN 3.3 VO 0.5-A to 1-A Step
LMZ14201 30114665.gif
Figure 28. Current Limit 1.8 VOUT at 25°C
LMZ14201 30114668.gif
Figure 30. Current Limit 3.3 VOUT at 85°C