SNVS648J January   2010  – October 2015 LMZ14202

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Constant On-Time Control (COT) Circuit Overview
      2. 7.3.2 Output Overvoltage Comparator
      3. 7.3.3 Current Limit
      4. 7.3.4 Thermal Protection
      5. 7.3.5 Zero Coil Current Detection
      6. 7.3.6 Prebiased Start-Up
    4. 7.4 Device Functional Modes
      1. 7.4.1 Discontinuous Conduction and Continuous Conduction Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Design Steps for the LMZ14202 Application
          1. 8.2.2.1.1 Enable Divider, RENT and RENB Selection
          2. 8.2.2.1.2 Output Voltage Selection
          3. 8.2.2.1.3 Soft-Start Capacitor Selection
          4. 8.2.2.1.4 CO Selection
          5. 8.2.2.1.5 Input Capacitance (CIN) Selection
          6. 8.2.2.1.6 RDS(on) Resistor Selection
            1. 8.2.2.1.6.1 Discontinuous Conduction and Continuous Conduction Mode Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation and Board Thermal Requirements
    4. 10.4 Power Module SMT Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules.

  • Minimize area of switched current loops. Wehn considering EMI reduction, it is imperative to minimize the high di/dt paths during PC board layout. The high-current loops that do not overlap have high di/dt content that cause observable high frequency noise on the output pin if the input capacitor (CIN1) is placed at a distance away from the LMZ14202. Therefore place CIN1 as close as possible to the LMZ14202 VIN and GND exposed thermal pad. This placement minimizes the high di/dt area and reduce radiated EMI. Additionally, ensure that grounding for both the input and output capacitor consists of a localized top side plane that connects to the GND exposed thermal pad (EP).
  • Have a single point ground. Route the ground connections for the feedback, soft-start, and enable components to the GND pin of the device. This routing prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to the exposed thremal pad.
  • Minimize trace length to the FB pin. Place both feedback resistors, RFBT and RFBB, and the feed forward capacitor CFF, close to the FB pin. Because the FB node is high impedance, maintain the copper area as small as possible. To minimize noise, route the traces from RFBT, RFBB, and CFF away from the body of the LMZ14202 device.
  • Make input and output bus connections as wide as possible. Width reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load to correct for voltage drops and provide optimum output accuracy.
  • Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter of 10 mils (254 μm) thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to maintain the junction temperature below 125°C.

10.2 Layout Example

LMZ14202 30114511.gif Figure 38. Minimize Area of Current Loops in Buck Module
LMZ14202 LMZ1420X_Layout.gif Figure 39. PCB Layout Guide
LMZ14202 30114516.png Figure 40. EVM Board Layout - Top View
LMZ14202 30114517.png Figure 41. EVM Board Layout - Bottom View

10.3 Power Dissipation and Board Thermal Requirements

When VIN = 24 V, VO = 3.3 V, IO = 2 A, TA(max) = 85°C , and TJ = 125°C, the device must achieve a thermal resistance from case-to-ambient described by Equation 18.

Equation 18. RθCA < (TJ(max) – TA(max)) / PIC-LOSS – RθJC

Given the typical thermal resistance from junction to case to be 1.9 °C/W, use the 85°C power dissipation curves in Typical Characteristics to estimate the PIC-LOSS for the application. In this application it is 1.5 W.

Equation 19. RθCA = (125 – 85) / (1.5 W – 1.9) = 24.8

To reach RθCA = 24.8, the PCB is required to dissipate heat effectively. With no airflow and no external heat, use Equation 20 to estimate the required board area covered by 1 oz. copper on both the top and bottom metal layers.

Equation 20. Board Area_cm2 = 500°C × cm2/W / RθJC

As a result, approximately 20.2 square cm of 1 oz copper on top and bottom layers is required for the PCB design. The PCB copper heat sink must be connected to the exposed pad. Approximately thirty-six, 10 mils (254 μm) thermal vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an example of a high thermal performance PCB layout, refer to the AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422) .

10.4 Power Module SMT Guidelines

The recommendations below are for a standard module surface mount assembly

  • Land Pattern Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
  • Stencil Aperture
    • For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern
    • For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
  • Solder Paste Use a standard SAC Alloy such as SAC 305, type 3 or higher
  • Stencil Thickness: 0.125 to 0.15 mm
  • Reflow: Refer to solder paste supplier recommendation and optimized per board size and density
    • Refer to AN SNAA214 for reflow information
    • Maximum number of reflows allowed is one
LMZ14202 reflow_chart_snvs632.png Figure 42. Sample Reflow Profile

Table 3. Sample Reflow Profile Table

Probe Max Temp (°C) Reached Max Temp Time Above 235°C Reached 235°C Time Above 245°C Reached 245°C Time Above 260°C Reached 260°C
#1 242.5 6.58 0.49 6.39 0.00 – 0.00 –
#2 242.5 7.10 0.55 6.31 0.00 7.10 0.00 –
#3 241.0 7.09 0.42 6.44 0.00 – 0.00 –