SNVS686K March   2011  – May 2024 LMZ22005

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Synchronization Input
      2. 6.3.2 Output Overvoltage Protection
      3. 6.3.3 Current Limit
      4. 6.3.4 Thermal Protection
      5. 6.3.5 Prebiased Start-Up
    4. 6.4 Device Functional Modes
      1. 6.4.1 Discontinuous And Continuous Conduction Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Design Steps
        2. 7.2.2.2 Enable Divider, RENT, RENB and RENH Selection
        3. 7.2.2.3 Output Voltage Selection
        4. 7.2.2.4 Soft-start Capacitor Selection
        5. 7.2.2.5 Tracking Supply Divider Option
        6. 7.2.2.6 CO Selection
        7. 7.2.2.7 CIN Selection
        8. 7.2.2.8 Discontinuous And Continuous Conduction Modes Selection
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Examples
    3. 9.3 Power Dissipation and Thermal Considerations
    4. 9.4 Power Module SMT Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. A good example layout is shown in Figure 9-3.

  1. Minimize area of switched current loops.

    From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout as shown in Figure 9-1. The high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input capacitor (CIN1) is placed at a distance away from the LMZ22005. Therefore place CIN1 as close as possible to the LMZ22005 VIN and PGND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a localized top side plane that connects to the PGND exposed pad (EP).

  2. Have a single point ground.

    The ground connections for the feedback, soft-start, and enable components should be routed to the AGND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Additionally provide the single point ground connection from pin 4 (AGND) to EP/PGND.

  3. Minimize trace length to the FB pin.

    Both feedback resistors, RFBT and RFBB, and the feed-forward capacitor CFF, must be located close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The traces from RFBT, RFBB, and CFF must be routed away from the body of the LMZ22005 to minimize possible noise pickup.

  4. Make input and output bus connections as wide as possible.

    This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and provide optimum output accuracy.

  5. Provide adequate device heat-sinking.

    Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 × 10 via array with a minimum via diameter of 8 mils thermal vias spaced 39 mils (1.0 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C.