SLVSBV7E June   2013  – February 2020 LMZ31707

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Application
  4. 4 Revision History
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Package Specifications
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
  6. 6 Device Information
    1. 6.1 Functional Block Diagram
    2.     Pin Functions
  7. 7 Typical Characteristics (PVIN = VIN = 12 V)
  8. 8 Typical Characteristics (PVIN = VIN = 5 V)
  9. 9 Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)
  10. 10Application Information
    1. 10.1  Adjusting the Output Voltage
    2. 10.2  Capacitor Recommendations for the LMZ31707 Power Supply
      1. 10.2.1 Capacitor Technologies
        1. 10.2.1.1 Electrolytic, Polymer-Electrolytic Capacitors
        2. 10.2.1.2 Ceramic Capacitors
        3. 10.2.1.3 Tantalum, Polymer-Tantalum Capacitors
      2. 10.2.2 Input Capacitor
      3. 10.2.3 Output Capacitor
    3. 10.3  Transient Response
    4. 10.4  Transient Waveforms
    5. 10.5  Application Schematics
    6. 10.6  Custom Design With WEBENCH® Tools
    7. 10.7  VIN and PVIN Input Voltage
    8. 10.8  3.3 V PVIN Operation
    9. 10.9  Power Good (PWRGD)
    10. 10.10 SYNC_OUT
    11. 10.11 Parallel Operation
    12. 10.12 Light Load Efficiency (LLE)
    13. 10.13 Power-Up Characteristics
    14. 10.14 Pre-Biased Start-up
    15. 10.15 Remote Sense
    16. 10.16 Thermal Shutdown
    17. 10.17 Output On/Off Inhibit (INH)
    18. 10.18 Slow Start (SS/TR)
    19. 10.19 Overcurrent Protection
    20. 10.20 Synchronization (CLK)
    21. 10.21 Sequencing (SS/TR)
    22. 10.22 Programmable Undervoltage Lockout (UVLO)
    23. 10.23 Layout Considerations
    24. 10.24 EMI
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 7 A,
CIN = 0.1 µF + 2 x 22 µF ceramic + 100 µF bulk, COUT = 4 x 47 µF ceramic (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOUT Output current TA = 85°C, natural convection 0 7 A
VIN Input bias voltage range Over output current range 4.5 17 V
PVIN Input switching voltage range Over output current range 2.95(3) 17(4) V
UVLO VIN Undervoltage lockout VIN Increasing 4.0 4.5 V
VIN Decreasing 3.5 3.85
VOUT(adj) Output voltage adjust range Over output current range 0.6 5.5 V
VOUT Set-point voltage tolerance TA = 25°C, IOUT = 0 A ±1%(2)
Temperature variation –40°C ≤ TA ≤ +85°C, IOUT = 0 A ±0.2%
Line regulation Over input voltage range ±0.1%
Load regulation Over output current range ±0.2%
Total output voltage variation Includes set-point, line, load, and temperature variation ±1.5%(2)
η Efficiency PVIN = VIN = 12 V
IO = 4 A  		 VOUT = 5.0 V, fSW = 1 MHz 94 %
VOUT = 3.3 V, fSW = 750 kHz 92 %
VOUT = 2.5 V, fSW = 750 kHz 90 %
VOUT = 1.8 V, fSW = 500 kHz 89 %
VOUT = 1.2 V, fSW = 300 kHz 87 %
VOUT = 0.9 V, fSW = 250 kHz 85 %
VOUT = 0.6 V, fSW = 200 kHz 82 %
PVIN = VIN = 5 V
IO = 4 A  		 VOUT = 3.3 V, fSW = 750 kHz 95 %
VOUT = 2.5 V, fSW = 750 kHz 93 %
VOUT = 1.8 V, fSW = 500 kHz 92 %
VOUT = 1.2 V, fSW = 300 kHz 90 %
VOUT = 0.9 V, fSW = 250 kHz 87 %
VOUT = 0.6 V, fSW = 200 kHz 84 %
Output voltage ripple 20 MHz bandwith 14 mVP-P
ILIM Current limit threshold ILIM pin open 12 A
ILIM pin to AGND 9 A
Transient response 1.0 A/µs load step from
25 to 75% IOUT(max) 		 Recovery time tbd µs
VOUT over/undershoot tbd mV
VINH Inhibit threshold voltage Inhibit High Voltage 1.3 open(5) V
Inhibit Low Voltage -0.3 1.1
IINH INH Input current VINH < 1.1 V -1.15 μA
INH Hysteresis current VINH > 1.3 V -3.3 μA
II(stby) Input standby current INH pin to AGND 2 10 µA
Power Good PWRGD Thresholds VOUT rising Good 95%
Fault 108%
VOUT falling Fault 91%
Good 104%
PWRGD Low Voltage I(PWRGD) = 0.5 mA 0.3 V
fSW Switching frequency RRT = 169 kΩ 400 500 600 kHz
fCLK Synchronization frequency CLK Control 200 1200 kHz
VCLK-H CLK High-Level 2.0 5.5 V
VCLK-L CLK Low-Level 0.5 V
DCLK CLK Duty Cycle 20 50 80 %
Thermal Shutdown Thermal shutdown 175 °C
Thermal shutdown hysteresis 10 °C
CIN External input capacitance Ceramic 44(6) µF
Non-ceramic 100(6)
COUT External output capacitance Ceramic 47(7) 200 1500 µF
Non-ceramic 220(7) 5000(8)
Equivalent series resistance (ESR) 35 mΩ
(1) See the Light Load Efficiency (LLE) section for more information for output voltages < 1.5 V.
(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.
(3) The minimum PVIN is 2.95 V or (VOUT + 0.7 V), whichever is greater. See for more details.
(4) The maximum PVIN voltage is 17 V or (22 x VOUT), whichever is less. See for more details.
(5) This pin has an internal pullup. If it is left open, the device operates when input power is applied. A small, low-leakage MOSFET is recommended for control. When the device is operating and no UVLO resistor divider is present on this pin, the open voltage is typically 2.9 V.
(6) A minimum of 44 µF of external ceramic capacitance is required across the input (VIN and PVIN connected) for proper operation. An additional 100 µF of bulk capacitance is recommended. It is also recommended to place a 0.1 µF ceramic capacitor directly across the PVIN and PGND pins of the device. Locate the input capacitance close to the device. When operating with split VIN and PVIN rails, place 4.7 µF of ceramic capacitance directly at the VIN pin. See Table 4 for more details.
(7) The amount of required output capacitance varies depending on the output voltage (see Table 3). The amount of required capacitance must include at least 1x 47-µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 3 and Table 4 more details.
(8) When using both ceramic and non-ceramic output capacitors, the combined maximum must not exceed 5000 µF. It may be necessary to increase the slow start time when turning on into the maximum capacitance. See the Slow Start (SS/TR) section for information on adjusting the slow start time.