SNVSB53C February   2018  – March 2023 LMZM23600

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Scheme
      2. 8.3.2 Soft-Start Function
      3. 8.3.3 Enable and External UVLO Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Power Good (PGOOD) Function
      7. 8.3.7 MODE/SYNC Function
        1. 8.3.7.1 Forced PWM Mode
        2. 8.3.7.2 Auto PFM Mode
        3. 8.3.7.3 Dropout Mode
        4. 8.3.7.4 SYNC Operation
      8. 8.3.8 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown
      2. 8.4.2 FPWM Operation
      3. 8.4.3 Auto PFM Mode Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Maximum Input Voltage for VOUT < 2.5 V
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Input Capacitor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Feedback Voltage Divider for Adjustable Output Voltage Versions
        5. 9.2.2.5 RPU - PGOOD Pullup Resistor
        6. 9.2.2.6 VIN Divider and Enable
      3. 9.2.3 Application Curves
        1. 9.2.3.1 VOUT = 5 V
        2. 9.2.3.2 VOUT = 3.3 V
        3. 9.2.3.3 VOUT = 12 V
        4. 9.2.3.4 VOUT = 15 V
        5. 9.2.3.5 VOUT = 2.5 V
        6. 9.2.3.6 VOUT = 1.2 V and VOUT = 1.8 V
        7. 9.2.3.7 VOUT = 5 V and 3.3 V Fixed Output Options
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Supply Voltage Range
      2. 9.4.2 Supply Current Capability
      3. 9.4.3 Supply Input Connections
        1. 9.4.3.1 Voltage Drops
        2. 9.4.3.2 Stability
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Thermal Design
      2. 9.5.2 Layout Examples
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.7.4 SYNC Operation

Synchronizing the switching frequency of multiple regulators in a single system is often desirable. This technique results in better defined EMI behavior and can reduce the need for capacitance on some power rails. The LMZM23600 MODE/SYNC input allows synchronization to an external clock. The LMZM23600 implements an in-phase locking scheme – the rising edge of the clock signal provided to the input of the LMZM23600 device corresponds to turning on the high-side MOSFET device. This function is implemented using phase locking over a limited frequency range eliminating large glitches upon initial application of an external clock. The clock fed into the LMZM23600 device replaces the internal free-running clock but does not affect frequency foldback operation. The foldback function takes over and the output voltage continues to be well regulated using frequency reduction when duty factors outside of the normal duty cycle range are reached. When the device is synchronized to the lower end of the synchronization range the internal inductor sees higher peak currents. For high current ripple designs (for example, high input voltage and 12-V and 15-V output designs), the maximum current capability of the device can be derated.

The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided.

The MODE/SYNC function logic always prioritizes the proper regulation of the output voltage. #GUID-84D14C1E-FC52-484E-844C-7C6E4FF0CD2A/T4606405-17 summarizes the MODE/SYNC function and the operating switching frequency with various conditions. See GUID-CE8EB451-1634-4063-9734-9C45FBC8CE23.html#GUID-CE8EB451-1634-4063-9734-9C45FBC8CE23 for frequency foldback vs input voltage behavior.

Table 8-1 Switching Frequency and MODE/SYNC Function
DEVICE SWITCHING FREQUENCY
MODE/SYNC LIGHT LOAD FULL LOAD VIN > 28 V IN DROPOUT MODE
ADJ Output Logic LOW = Auto PFM Reduced
(save power)		 Fixed
1000 kHz		 Reduced
(maintain regulation)		 Reduced
(maintain regulation)
Logic HIGH = FPWM Fixed
1000 kHz		 Fixed
1000 kHz		 Reduced
(maintain regulation)		 Reduced
(maintain regulation)
Valid FSYNC Input FSYNC
 FSYNC
 Reduced
(maintain regulation)		 Reduced
(maintain regulation)
Fixed
3.3-V Output
or 5-V Output		 Logic LOW = Auto PFM Reduced
(save power)		 Fixed
750 kHz		 Fixed
750 kHz		 Reduced
(maintain regulation)
Logic HIGH = FPWM Fixed
750 kHz		 Fixed
750 kHz		 Fixed
750 kHz		 Reduced
(maintain regulation)
Valid FSYNC Input FSYNC
 FSYNC
 FSYNC
 Reduced
(maintain regulation)