SNVSAQ4C December 2017 – March 2023 LMZM23601
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Synchronizing the switching frequency of multiple regulators in a single system is often desirable. This technique results in better defined EMI behavior and can reduce the need for capacitance on some power rails. The LMZM23601 MODE/SYNC input allows synchronization to an external clock. The LMZM23601 implements an in-phase locking scheme – the rising edge of the clock signal provided to the input of the LMZM23601 device corresponds to turning on the high-side MOSFET device. This function is implemented using phase locking over a limited frequency range eliminating large glitches upon initial application of an external clock. The clock fed into the LMZM23601 device replaces the internal free-running clock but does not affect frequency foldback operation. The foldback function takes over and the output voltage continues to be well regulated using frequency reduction when duty factors outside of the normal duty cycle range are reached. When the device is synchronized to the lower end of the synchronization range the internal inductor sees higher peak currents. For high current ripple designs (for example, high input voltage and 12-V and 15-V output designs), the maximum current capability of the device can be derated.
The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided.
The MODE/SYNC function logic always prioritizes the proper regulation of the output voltage. #GUID-84D14C1E-FC52-484E-844C-7C6E4FF0CD2A/T4606405-17 summarizes the MODE/SYNC function and the operating switching frequency with various conditions. See GUID-CE8EB451-1634-4063-9734-9C45FBC8CE23.html#GUID-CE8EB451-1634-4063-9734-9C45FBC8CE23 for frequency foldback vs input voltage behavior.
DEVICE | SWITCHING FREQUENCY | ||||
---|---|---|---|---|---|
MODE/SYNC | LIGHT LOAD | FULL LOAD | VIN > 28 V | IN DROPOUT MODE | |
ADJ Output | Logic LOW = Auto PFM | Reduced (save power) |
Fixed 1000 kHz |
Reduced (maintain regulation) |
Reduced (maintain regulation) |
Logic HIGH = FPWM | Fixed 1000 kHz |
Fixed 1000 kHz |
Reduced (maintain regulation) |
Reduced (maintain regulation) |
|
Valid FSYNC Input | FSYNC |
FSYNC |
Reduced (maintain regulation) |
Reduced (maintain regulation) |
|
Fixed 3.3-V Output or 5-V Output |
Logic LOW = Auto PFM | Reduced (save power) |
Fixed 750 kHz |
Fixed 750 kHz |
Reduced (maintain regulation) |
Logic HIGH = FPWM | Fixed 750 kHz |
Fixed 750 kHz |
Fixed 750 kHz |
Reduced (maintain regulation) |
|
Valid FSYNC Input | FSYNC |
FSYNC |
FSYNC |
Reduced (maintain regulation) |