SLVSAW6H June   2011  – November 2024 LP2951-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Both Legacy and New Chip)
    6. 5.6 Timing Requirements (New Chip only)
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reverse Current
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Estimating Junction Temperature
      4. 7.1.4 Power Dissipation (PD)
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Recommended Capacitor Types
          1. 7.2.1.1.1 Recommended Capacitors (Legacy Chip)
            1. 7.2.1.1.1.1 ESR Range (Legacy Chip)
          2. 7.2.1.1.2 Recommended Capacitors (New Chip)
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Feedback Resistor Selection
        2. 7.2.2.2 Feedforward Capacitor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.3 Application Curves

LP2951-Q1 Line Transient Response vs Time (Legacy Chip)
 
Figure 7-5 Line Transient Response vs Time (Legacy Chip)
LP2951-Q1 Load Transient Response vs Time (Legacy Chip)
VOUT = 5V, CL = 10µF 
Figure 7-7 Load Transient Response vs Time (Legacy Chip)
LP2951-Q1 Load Transient Response vs Time (New Chip)
VIN = 6V, VOUT = 5V, IL = 0mA to 100mA, CL = 1μF
Figure 7-9 Load Transient Response vs Time (New Chip)
LP2951-Q1 Enable Transient Response vs Time (New Chip)
VIN = 6V, VOUT = 5V, CL = 1μF, IL = 1mA
Figure 7-11 Enable Transient Response vs Time (New Chip)
LP2951-Q1 Enable Transient Response vs Time (New Chip)
VIN = 6V, VOUT = 5V, CL = 10μF, IL = 1mA
Figure 7-13 Enable Transient Response vs Time (New Chip)
LP2951-Q1 Line Transient Response vs Time (New Chip)
VIN = 6V to 8V, VOUT = 5V, CL = 1μF, IL = 100μA
Figure 7-6 Line Transient Response vs Time (New Chip)
LP2951-Q1 Load Transient Response vs Time (New Chip)
VIN = 6V, VOUT = 5V, IL = 0mA to 100mA, CL = 10μF
Figure 7-8 Load Transient Response vs Time (New Chip)
LP2951-Q1 Enable Transient Response vs Time (Legacy Chip)
IL = 1mA, CL = 1µF 
Figure 7-10 Enable Transient Response vs Time (Legacy Chip)
LP2951-Q1 Enable Transient Response vs Time
IL = 1mA, CL = 10µF 
Figure 7-12 Enable Transient Response vs Time