SLVSAW6G June   2011  – April 2024 LP2951-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 ERROR Function
      2. 6.3.2 Programming Output Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Input Capacitor (CIN)
        2. 7.2.1.2 Output Capacitor (COUT)
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Capacitance Value
        2. 7.2.2.2 Capacitor Types
        3. 7.2.2.3 CBYPASS: Noise and Stability Improvement
        4. 7.2.2.4 ESR Range
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2 Programming Output Voltage

A unique feature of the LP2951-Q1 is the ability to output either a fixed voltage or an adjustable voltage, depending on the external pin connections. To output the internally programmed fixed voltage, tie the SENSE pin to the OUTPUT pin and the FEEDBACK pin to the VTAP pin. Alternatively, a user-programmable voltage ranging from the internal 1.235-V reference to a 30-V max can be set by using an external resistor divider pair. The resistor divider is tied to VOUT, and the divided-down voltage is tied directly to FEEDBACK for comparison against the internal 1.235-V reference. To satisfy the steady-state condition in which the two inputs are equal, the error amplifier drives the output to equal Equation 1:

Equation 1. GUID-05D03EFA-94EB-48FA-B32B-E0BE561E7D46-low.gif

where:

  • VREF = 1.235 V applied across R2 (see Figure 6-2)
  • IFB = FEEDBACK bias current, typically 20 nA

A minimum regulator output current of 1 μA must be maintained. Thus, in an application where a no-load condition is expected (for example, CMOS circuits in standby), this 1-μA minimum current must be provided by the resistor pair, effectively imposing a maximum value of R2 = 1.2 MΩ (1.235 V / 1.2 MΩ ≉ 1 μA).

IFB = 20 nA introduces an error not approximately equal to 0.02% in VOUT. This error can be offset by trimming R1. Alternatively, increasing the divider current makes IFB less significant, thus, reducing the error contribution. For instance, using R2 = 100 kΩ reduces the error contribution of IFB to 0.17% by increasing the divider current to not approximately equal to 12 μA. This increase in the divider current still is small compared to the 600-μA typical quiescent current of the LP2951-Q1 under no load.

GUID-8E503C67-B25D-4F84-A547-8E053227E4CB-low.gif Figure 6-2 Adjusting the Feedback on the LP2951-Q1