SLVSAW6H June   2011  – November 2024 LP2951-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Both Legacy and New Chip)
    6. 5.6 Timing Requirements (New Chip only)
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reverse Current
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Estimating Junction Temperature
      4. 7.1.4 Power Dissipation (PD)
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Recommended Capacitor Types
          1. 7.2.1.1.1 Recommended Capacitors (Legacy Chip)
            1. 7.2.1.1.1.1 ESR Range (Legacy Chip)
          2. 7.2.1.1.2 Recommended Capacitors (New Chip)
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Feedback Resistor Selection
        2. 7.2.2.2 Feedforward Capacitor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics (Both Legacy and New Chip)

VIN = VOUT (nominal) + 1V, IL = 100µA, CL = 1µF (for new chip) and CL = 2.2µF (for legacy chip),
FEEDBACK tied to VTAP, OUTPUT tied to SENSE, VSHUTDOWN ≤ 0.7V
PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT
3.3-V VERSION
Output voltage IL = 100µA Legacy chip 25°C 3.267 3.3 3.333 V
–40°C to 125°C 3.234 3.3 3.366
New chip 25°C 3.2868 3.3 3.3132
–40°C to 125°C 3.2736 3.3 3.3264
5-V VERSION
Output voltage IL = 100µA Legacy chip 25°C 4.95 5 5.05 V
–40°C to 125°C 4.900 5 5.100
New chip 25°C 4.98 5 5.02
–40°C to 125°C 4.96 5 5.04
Output voltage accuracy VIN = [VOUT(NOM) + 1V] to 30V, IL = 100µA to 100mA New chip –40°C to 125°C –1 1 %
Output voltage temperature coefficient(1) IL = 100µA Legacy chip –40°C to 125°C 20 100 ppm/°C
New chip 20 60
Line regulation(2) VIN = [VOUT(NOM) + 1 V] to 30V Legacy chip 25°C 0.03 0.2 %/V
–40°C to 125°C 0.4
New chip 25°C 0.0006 0.01
–40°C to 125°C 0.015
Load regulation(2) IL = 100µA to 100mA Legacy chip 25°C 0.04 0.2 %
–40°C to 125°C 0.3
New chip 25°C 0.04 0.1
–40°C to 125°C 0.2
Dropout voltage VIN = 2V, IL = 100µA Legacy chip 25°C 50 80 mV
–40°C to 125°C 150
New chip 25°C 1 4
–40°C to 125°C 5
VIN = 2V, IL = 100mA Legacy chip 25°C 380 450
–40°C to 125°C 600
New chip 25°C 340 420
–40°C to 125°C 550
GND current IL = 100µA Legacy chip 25°C 75 120 µA
–40°C to 125°C 140
New chip 25°C 50 65
–40°C to 125°C 80
IL = 100mA Legacy chip 25°C 8 12 mA
–40°C to 125°C 14
New chip 25°C 0.8
–40°C to 125°C 0.9
Dropout ground current VIN = VOUT(NOM) – 0.5V,
IL = 100µA		 Legacy chip 25°C 110 170 µA
–40°C to 125°C 200
New chip 25°C 78 120
–40°C to 125°C 150
UVLO VIN rising IL = 100µA New chip –40°C to 125°C 1.8 1.9 2.0 V
UVLO VIN falling 1.7 1.8 1.9
Hysteresis 100 mV
Current limit VOUT = 0V Legacy chip 25°C 160 200 mA
–40°C to 125°C 220
New chip 25°C 180 200
–40°C to 125°C 230
Thermal regulation(3) IL = 100µA Legacy chip 25°C 0.05 0.2 %/W
New chip 0.05 0.2
Output noise (RMS),
10Hz to 100KHz		 CL = 1µF (5V only) Legacy chip 25°C 430 µV
New chip 265
CL = 200µF Legacy chip 25°C 160
CL = 100µF New chip 250
CL = 3.3µF,
CBypass = 0.01µF between
pins 1 and 7		 Legacy chip 25°C 100
New chip 100
Power supply ripple rejection VIN - VOUT = 1V, frequency = 100Hz, IOUT ≥ 5mA New chip 25°C 80 dB
 ADJ VERSION 
Reference voltage VIN = 2.3V to 30V,
IL = 100µA to 100mA		 Legacy chip –40°C to 125°C 1.2 1.272 V
New chip 1.188 1.212
Reference voltage temperature coefficient(1) Legacy chip 25°C 20 ppm/°C
New chip 5
FEEDBACK bias current New chip 25°C 10 50 nA
–40°C to 125°C 60
FEEDBACK bias current temperature coefficient New chip 25°C 0.1 nA/°C
ERROR COMPARATOR
Output leakage current VOUT = 30V Legacy chip 25°C 0.01 1 µA
–40°C to 125°C 2
New chip 25°C 0.2 0.5
–40°C to 125°C 1
Output low voltage VIN ≥ 2V
IOL = 400µA		 Legacy chip 25°C 150 250 mV
–40°C to 125°C 400
New chip 25°C 180 250
–40°C to 125°C 350
Upper threshold voltage (ERROR output high)(4) Legacy chip 25°C 40 60 mV
–40°C to 125°C 25
New chip 25°C 40 60
–40°C to 125°C 25
Lower threshold voltage (ERROR output low)(4) Legacy chip 25°C 75 95 mV
–40°C to 125°C 140
New chip 25°C 75 95
–40°C to 125°C 140
Hysteresis(4) Legacy chip 25°C 15 mV
New chip 15
SHUTDOWN INPUT
Input logic voltage Low (regulator ON) Legacy chip –40°C to 125°C 0.7 V
New chip 0.7
High (regulator OFF) Legacy chip –40°C to 125°C 2
New chip 2
SHUTDOWN input current SHUTDOWN = 2.4V Legacy chip 25°C 30 50 µA
–40°C to 125°C 100
New chip 25°C 0.2 0.5
–40°C to 125°C 1
SHUTDOWN = 30V Legacy chip 25°C 450 600
–40°C to 125°C 750
New chip 25°C 0.3 0.5
–40°C to 125°C 1
Regulator output current
in shutdown		 VSHUTDOWN ≥ 2V,
VIN ≥ 30V, VOUT = 0,
FEEDBACK tied to VTAP		 Legacy chip 25°C 3 10 µA
–40°C to 125°C 20
New chip 25°C 4 6
–40°C to 125°C 7.5
(1) Output or reference voltage temperature coefficient is defined as the worst-case voltage change divided by the total temperature range.
(2) Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to heating effects are covered under the specification for thermal regulation.
(3) Thermal regulation is defined as the change in output voltage at a time (T) after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for a 50-mA load pulse at VIN = 30V, VOUT = 5V (1.25W pulse) for t = 10ms.
(4) Comparator thresholds are expressed in terms of a voltage differential equal to the nominal reference voltage (measured at VIN – VOUT = 1V) minus FEEDBACK terminal voltage. To express these thresholds in terms of output voltage change, multiply by the error amplifier gain = VOUT/VREF = (R1 + R2)/R2. For example, at a programmed output voltage of 5V, the ERROR output is specified to go low when the output drops by 95mV × 5V/1.2V = 395mV. Thresholds remain constant as a percentage of VOUT (as VOUT is varied), with the low-output warning occurring at 6% below nominal (typ) and 7.7%(max).