SNVS001F april   2000  – july 2023 LP2980-ADJ

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage
      3. 7.3.3 Current Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Output Pulldown
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Feedback Resistors
      2. 8.1.2 Recommended Capacitor Types
        1. 8.1.2.1 Recommended Capacitors for the New Chip
        2. 8.1.2.2 Recommended Capacitors for the Legacy Chip
      3. 8.1.3 Input and Output Capacitor Requirements
      4. 8.1.4 Feed-Forward Capacitor (CFF)
      5. 8.1.5 Reverse Current
      6. 8.1.6 Power Dissipation (PD)
      7. 8.1.7 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting VOUT For the LP2980-ADJ LDO
        2. 8.2.2.2 ON/OFF Input Operation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20230604-SS0I-8PH4-Z2SK-7MGXZGLQSCVX-low.svg Figure 5-1 DBV Package,5-Pin SOT-23(Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
ADJ 4 I/O Feedback pin to set the output voltage with help of the feedback divider. See the Recommended Operating Conditions section for more information.
GND 2 — Ground
ON/OFF 3 I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the Electrical Characteristics table. Tie this pin to VIN if unused.
VIN 1 I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the Input and Output Capacitor Requirements section for more information.
VOUT 5 O Output of the regulator. Use a capacitor with a value of 4.7 µF (for legacy chip) and 2.2 μF (for new chip) or larger from this pin to ground.(1) See the Input and Output Capacitor Requirements section for more information.
(1) The nominal output capacitance must be greater than 1 μF (for the new chip) and 2.2 μF (for the legacy chip). Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF (for the new chip) and 2.2 μF (for the legacy chip).