SLVS522R july   2004  – july 2023 LP2985 , LP2985A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage
      3. 7.3.3 Current Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Output Pulldown
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Input and Output Capacitor Requirements
      3. 8.1.3 Noise Bypass Capacitor (CBYPASS)
      4. 8.1.4 Reverse Current
      5. 8.1.5 Power Dissipation (PD)
      6. 8.1.6 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ON/OFF Operation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • VIN range (new chip): 2.5 V to 16 V
  • VOUT range (new chip):
    • 1.2 V to 5.0 V (fixed, 100-mV steps)
  • VOUT accuracy:
    • ±1% for A-grade legacy chip
    • ±1.5% for standard-grade legacy chip
    • ±0.5% for new chip only
  • ±1% output accuracy over load, and temperature for new chip
  • Output current: Up to 150 mA
  • Low IQ (new chip): 71 μA at ILOAD = 0 mA
  • Low IQ (new chip): 750 μA at ILOAD = 150 mA
  • Shutdown current:
    • 0.01 μA (typ) for legacy chip
    • 1.12 μA (typ) for new chip
  • Low noise: 30 μVRMS with 10-nF bypass capacitor
  • Output current limiting and thermal protection
  • Stable with 2.2-µF ceramic capacitors
  • High PSRR: 70 dB at 1 kHz, 40 dB at 1 MHz
  • Operating junction temperature: –40°C to +125°C
  • Package: 5-pin SOT-23 (DBV)