SNVS086K May   2000  – July 2015 LP2989LV

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Accuracy Output Voltage
      2. 7.3.2 Sleep Mode
      3. 7.3.3 Error Detection Comparator Output
      4. 7.3.4 Short Circuit Protection (Current Limit)
      5. 7.3.5 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With 16 V ≥ VIN > VOUT(TARGET) + 1 V
      2. 7.4.2 Operation with Shutdown Control
      3. 7.4.3 Shutdown Input Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 WSON Package Devices
        2. 8.2.2.2 External Capacitors
          1. 8.2.2.2.1 Input Capacitor
          2. 8.2.2.2.2 Output Capacitor
          3. 8.2.2.2.3 Noise Bypass Capacitor
        3. 8.2.2.3 Capacitor Characteristics
          1. 8.2.2.3.1 Ceramic
          2. 8.2.2.3.2 Tantalum
          3. 8.2.2.3.3 Film
        4. 8.2.2.4 Reverse Input-Output Voltage
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions


D Package
8-Pin SOIC
Top View
LP2989LV cd_m08a_mua08a_snvs083.png
NGN Package
8-Lead WSON
Top View
LP2989LV cd_ldc08a_snvs083.png

Pin Functions

PIN I/O DESCRIPTION
NAME NUMBER
BYPASS 1 I Bypass capacitor input
ERROR 7 O Error signal output
GROUND 3 — GND
INPUT 4 I Regulator power input
N/C 2 — DO NOT CONNECT. Device pin 2 is reserved for post packaging test and calibration of the LP2989LV VOUT accuracy. Device pin 2 must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 2 is discouraged. Continuity test results are variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 2 may activate the trim circuitry forcing VOUT to move out of tolerance.
OUTPUT 5 O Regulated output voltage
SENSE 6 I Feedback voltage sense input
SHUTDOWN 8 I Shutdown input
Thermal Pad — — The exposed thermal pad on the bottom of the WSON package must be connected to a copper thermal pad on the PCB under the package. The use of thermal vias to remove heat from the package into the PCB is recommended. Connect the thermal pad to ground potential or leave floating. Do not connect the thermal pad to any potential other than the same ground potential seen at device pin 3. For additional information on using TI's Non Pull Back WSON package, see Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401).