SNVS521K December   2007  – August 2014 LP2998 , LP2998-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Descriptions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings: LP2998
    3. 7.3 Handling Ratings: LP2998-Q1
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Capacitor
      2. 9.1.2 Output Capacitor
      3. 9.1.3 Thermal Dissipation
    2. 9.2 Typical Application
      1. 9.2.1 DDR-III Applications
      2. 9.2.2 DDR-II Applications
      3. 9.2.3 SSTL-2 Applications
      4. 9.2.4 Level Shifting
        1. 9.2.4.1 Output Capacitor Selection
      5. 9.2.5 HSTL Applications
      6. 9.2.6 QDR Applications
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

  1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.
  2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For motherboard applications an ideal location would be at the center of the termination bus.
  3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference voltage.
  4. For improved thermal performance excessive top side copper should be used to dissipate heat from the package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these can be located underneath the package if manufacturing standards permit.
  5. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A 0.1 µF ceramic capacitor located close to the SENSE can also be used to filter any unwanted high frequency signal. This can be an issue especially if long SENSE traces are used.
  6. VREF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This capacitor should be located as close as possible to the VREF pin.

11.2 Layout Examples

Figure 31 and Figure 32 are layout examples for the LP2998/Q1. These examples are taken from the LP2998EVM.

layout_01_snoscy7.pngFigure 31. LP2998EVM SO PowerPAD Layout Example (Front)
layout_02_snoscy7.pngFigure 32. LP2998EVM SO PowerPAD Layout Example (Back)