SNVS003G June   1999  – April 2016 LP3470

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Reset Time-Out Period
      2. 7.2.2 Reset Output
      3. 7.2.3 Pullup Resistor Selection
      4. 7.2.4 Negative-Going VCC Transients
    3. 7.3 Device Functional Modes
      1. 7.3.1 Reset Output Low
      2. 7.3.2 Reset Output High
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VCC voltage –0.3 6 V
Reset voltage –0.3 6 V
Output current (Reset) 10 mA
Power dissipation (TA = 25°C)(3) 300 mW
Lead temperature (soldering, 5 sec) 260 °C
Junction temperature, TJMAX 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax − TA)/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Operating voltage 0.5 5.5 V
TA Operating temperature LP3470 –20 85 °C
LP3470I –40 85

6.4 Thermal Information

THERMAL METRIC(1) LP3470 UNIT
DBV (SOT-23)
5 PINS
RθJA Junction-to-ambient thermal resistance 171 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 124.8 °C/W
RθJB Junction-to-board thermal resistance 30.9 °C/W
ψJT Junction-to-top characterization parameter 17.9 °C/W
ψJB Junction-to-board characterization parameter 30.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Limits and typical numbers are for TJ = 25°C, and VCC = 2.4 V to 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VCC Operating voltage TJ = –20°C to 85°C 0.5 5.5 V
ICC VCC supply current VCC = 4.5 V TJ = 25°C 16 µA
TJ = –20°C to 85°C 30
VRTH Reset threshold voltage LP3470 0.99 × VRTH VRTH 1.01 × VRTH V
LP3470I TJ = 25°C 0.99 × VRTH VRTH 1.01 × VRTH
TJ = –40°C to 85°C 0.985 × VRTH 1.015 × VRTH
VHYST Hysteresis voltage(3) TJ = 25°C 35 mV
TJ = –20°C to 85°C 15 65
tPD VCC to reset delay VCC falling at 1 mV/µs TJ = 25°C 100 µs
TJ = –20°C to 85°C 300
tRP Reset time-out period(4) C1 = 1 nF TJ = 25°C 2 ms
TJ = –20°C to 85°C 1 3.5
VOL Reset output voltage low VCC = 0.5 V, IOL = 30 µA, TJ = –20°C to 85°C 0.1 V
VCC = 1 V, IOL = 100 µA, TJ = –20°C to 85°C 0.1
VCC =VRTH − 100 mV, IOL = 4 mA,
TJ = –20°C to 85°C		 0.4
R1 External pullup resistor 0.68 20 68 kΩ
ILEAK Reset output leakage current TJ = 25°C 0.15 1 µA
TJ = –20°C to 85°C 6
(1) Minimum and maximum limits in standard typeface are 100% production tested at 25°C. Minimum and maximum limits in full operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
(3) VHYST affects the relation between VCC and Reset as shown in the timing diagram.
(4) tRP is programmable by varying the value of the external capacitor (C1) connected to pin SRT. The equation is: tRP = 2000 × C1 (C1 in µF and tRP in ms).

6.6 Typical Characteristics

at TA = 25°C (unless otherwise noted)
LP3470 10001610.png Figure 1. ICC vs Temperature
LP3470 10001613.png Figure 3. VCC to Reset Delay vs Temperature
LP3470 10001608.png
Figure 5. Normalized VRTH vs Temperature
LP3470 10001614.png
Figure 7. VHYST vs VRTH
LP3470 10001611.png Figure 2. ICC vs VCC
LP3470 10001612.png Figure 4. Normalized tRP vs Temperature
LP3470 10001606.png
Figure 6. Transient Rejection
LP3470 10001609.png
Figure 8. VHYST vs Temperature