SNVSBF5C July   2019  – May 2020 LP3470A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Basic Operating Circuit
      2.      Typical Supply Current for LP3470A
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 RESET Time-Out Period
      2. 8.3.2 RESET Output
      3. 8.3.3 Pull-up Resistor Selection
      4. 8.3.4 VCC Transient Immunity
    4. 8.4 Device Functional Modes
      1. 8.4.1 RESET Output Low
      2. 8.4.2 RESET Output High
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 RESET Time-Out Period

The reset time delay can be set to a minimum value of 50 µs by leaving the SRT pin floating, or a maximum value of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (tD) can be programmed by connecting a capacitor no larger than 10 µF between SRT pin and GND.

The relationship between external capacitor (CSRT) in Farads at SRT pin and the time delay (tD) in seconds is given by Equation 1.

Equation 1. tD = -ln (0.29) x RSRT x CSRT + tD (no cap)

Equation 1 is simplified to Equation 2 by plugging RSRT and tD(no cap) given in Electrical Characteristics section:

Equation 2. tD = 618937 x CSRT + 50 µs

Equation 3 solves for external capacitor value (CSRT) in units of Farads where tD is in units of seconds

Equation 3. CSRT = (tD- 50 µs) ÷ 618937

The reset delay varies according to three variables: the external capacitor variance (CSRT), SRT pin internal resistance (RSRT) provided in the Electrical Characteristics table, and a constant. The minimum and maximum variance due to the constant is shown in Equation 5 and Equation 6.

Equation 4. tD (minimum) = -ln (0.36) x RSRT (min) x CSRT (min) + tD (no cap, min)
Equation 5. tD (maximum) = -ln (0.26) x RSRT (max) x CSRT (max) + tD (no cap, max)

The recommended maximum delay capacitor for the LP3470A is limited to 10 µF as this ensures there is enough time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above zero and the reset delay will be shorter than expected. Larger delay capacitors can be used so long as the capacitor has enough time to fully discharge during the duration of the voltage fault.