SNVSBF5C July   2019  – May 2020 LP3470A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Basic Operating Circuit
      2.      Typical Supply Current for LP3470A
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 RESET Time-Out Period
      2. 8.3.2 RESET Output
      3. 8.3.3 Pull-up Resistor Selection
      4. 8.3.4 VCC Transient Immunity
    4. 8.4 Device Functional Modes
      1. 8.4.1 RESET Output Low
      2. 8.4.2 RESET Output High
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

At 0.95 V ≤ VCC ≤ 10 V, SRT = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VCC, output reset load (CLOAD) = 10 pF and over the operating free-air temperature range – 40°C to 125°C, VCC slew rate < 100mV / us, unless otherwise noted. Typical values are at TJ = 25°C. 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tP_HL Propagation detect delay for VCC falling below VIT- VCC = VIT+ to (VIT-) - 10% (1) 15 30 µs
tD Reset time delay SRT pin = open
VCC = (VIT- -1V) to  (VIT+ + 1V)		 50 µs
SRT pin = 10 nF(2)(3) 6.2 ms
SRT pin = 1 µF(2)(3) 619 ms
tGI_VIT- Glitch immunity VIT- 5% VIT- overdrive(3)(4) 10 µs
(1) tP_HL measured from threhold trip point (VIT-) to VOL 
(2) Ideal capacitor
(3) Parameter is guranteed by design.
(4) Overdrive % = [(VCC/ VIT-) - 1] × 100%