SNVS321O January   2005  – December 2015 LP38691 , LP38691-Q1 , LP38693 , LP38693-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LP38691 and LP38693
    3. 6.3 ESD Ratings: LP38691-Q1 and LP38693-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Thermal Overload Protection (TSD)
      3. 7.3.3 Foldback Current Limiting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable (EN)
      2. 7.4.2 Minimum Operating Input Voltage (VIN)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reverse Voltage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Dissipation and Device Operation
        2. 8.2.2.2 External Capacitors
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Output Capacitor
        5. 8.2.2.5 No-Load Stability
        6. 8.2.2.6 Capacitor Characteristics
        7. 8.2.2.7 RFI/EMI Susceptibility
        8. 8.2.2.8 Output Noise
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 WSON Mounting
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The dynamic performance of the LP38691 or LP38693 is dependent on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the load regulation, PSRR, noise, or transient performance of the LP38691 or LP38693.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP38691 or LP38693, and as close to the package as is practical. The ground connections for CIN and COUT must be back to the LP38691 or LP38693 GND pin using as wide, and as short, a copper trace as is practical.

Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. These add parasitic inductances and resistance that result in inferior performance especially during transient conditions.

A Ground Plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly recommended. This Ground Plane serves two purposes:

  • Provides a circuit reference plane to assure accuracy.
  • Provides a thermal plane to remove heat from the LP38691 or LP38693 WSON package through thermal vias under the package DAP.

10.2 Layout Example

LP38691 LP38693 LP38691-Q1 LP38693-Q1 layoutto252.gif Figure 30. TO-252 Package
LP38691 LP38693 LP38691-Q1 LP38693-Q1 layoutwson.gif Figure 31. WSON LP38691 Layout

space

space

LP38691 LP38693 LP38691-Q1 LP38693-Q1 layoutsot223.gif
Figure 32. SOT-223 Layout
LP38691 LP38693 LP38691-Q1 LP38693-Q1 layoutwsonen.gif Figure 33. WSON LP38693 Layout

10.3 WSON Mounting

The NGG0006A (No Pullback) 6-Lead WSON package requires specific mounting techniques which are detailed in the TI AN-1187 Application Report SNOA401. Referring to the section PCB Design Recommendations, note that the pad style which must be used with the WSON package is the NSMD (non-solder mask defined) type. Additionally, TI recommends the PCB terminal pads to be 0.2 mm longer than the package pads to create a solder fillet to improve reliability and inspection.

The input current is split between two IN pins, 1 and 6. The two IN pins must be connected together to ensure that the device can meet all specifications at the rated current.

The thermal dissipation of the WSON package is directly related to the printed circuit board construction and the amount of additional copper area connected to the DAP.

The DAP (exposed pad) on the bottom of the WSON package is connected to the die substrate with a conductive die attach adhesive. The DAP has no direct electrical (wire) connection to any of the pins. There is a parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device lead 2 (that is, GND). Alternately, but not recommended, the DAP may be left floating (that is, no electrical connection). The DAP must not be connected to any potential other than ground.