SNVS321O January   2005  – December 2015 LP38691 , LP38691-Q1 , LP38693 , LP38693-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LP38691 and LP38693
    3. 6.3 ESD Ratings: LP38691-Q1 and LP38693-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Thermal Overload Protection (TSD)
      3. 7.3.3 Foldback Current Limiting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable (EN)
      2. 7.4.2 Minimum Operating Input Voltage (VIN)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reverse Voltage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Dissipation and Device Operation
        2. 8.2.2.2 External Capacitors
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Output Capacitor
        5. 8.2.2.5 No-Load Stability
        6. 8.2.2.6 Capacitor Characteristics
        7. 8.2.2.7 RFI/EMI Susceptibility
        8. 8.2.2.8 Output Noise
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 WSON Mounting
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

MIN MAX UNIT
Lead temp. (Soldering, 5 seconds) 260 °C
Power dissipation(3) Internally Limited V
V(max) All pins (with respect to GND) –0.3 12 V
IOUT(4) Internally Limited V
Junction temperature –40 150 °C
Storage temperature, Tstg −65 150
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
(3) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used). When using the WSON package, refer to AN-1187 Leadless Leadframe Package (LLP), SNOA401, and the WSON Mounting section in this datasheet. If power dissipation causes the junction temperature to exceed specified limits, the device goes into thermal shutdown.
(4) If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.

6.2 ESD Ratings: LP38691 and LP38693

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings: LP38691-Q1 and LP38693-Q1

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.4 Recommended Operating Conditions

MIN NOM MAX UNIT
VIN supply voltage 2.7 10 V
Operating junction temperature −40 125 °C

6.5 Thermal Information

THERMAL METRIC(1) LP38691 LP38693 LP3869x UNIT
TO-252 WSON SOT-223
3 PINS 6 PINS 5 PINS
RθJA(2) Junction-to-ambient thermal resistance 50.5 50.6 68.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.6 44.4 52.2 °C/W
RθJB Junction-to-board thermal resistance 29.7 24.9 13.0 °C/W
ψJT Junction-to-top characterization parameter 4.8 0.4 5.5 °C/W
ψJB Junction-to-board characterization parameter 29.3 25.1 12.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.5 5.4 n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Junction-to-ambient thermal resistance, High-K.

6.6 Electrical Characteristics

Unless otherwise specified, limits apply for TJ = 25°C, VIN = VOUT + 1 V, CIN = COUT = 10 µF, ILOAD = 10 mA. Minimum and maximum limits are specified through testing, statistical correlation, or design.
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VO Output voltage tolerance –2 2 %VOUT
100 µA < IL < 0.5 A
VO + 1 V ≤ VIN ≤ 10 V
Full operating temperature range		 –4 4
ΔVO/ΔVIN Output voltage line regulation(2) VO + 0.5 V ≤ VIN ≤ 10 V
IL = 25 mA		 0.03 %/V
VO + 0.5 V ≤ VIN ≤ 10 V
IL = 25 mA
Full operating temperature range		 0.1
ΔVO/ΔIL Output voltage load regulation(3) 1 mA < IL < 0.5 A
VIN = VO + 1 V		 1.8 %/A
1 mA < IL < 0.5 A
VIN = VO + 1 V
Full operating temperature range		 5
VIN – VOUT Dropout voltage(4) (VO = 2.5 V) IL = 0.1 A 80 mV
IL = 0.5 A 430
(VO = 2.5 V)
Full operating temperature range		 IL = 0.1 A 145
IL = 0.5 A 725
(VO = 3.3 V) IL = 0.1 A 65
IL = 0.5 A 330
(VO = 3.3 V)
Full operating temperature range		 IL = 0.1 A 110
IL = 0.5 A 550
(VO = 5 V) IL = 0.1 A 45
IL = 0.5 A 250
(VO = 5 V)
Full operating temperature range		 IL = 0.1 A 100
IL = 0.5 A 450
IQ Quiescent current VIN ≤ 10 V, IL =100 µA - 0.5 A 55 µA
VIN ≤ 10 V, IL =100 µA - 0.5 A
Full operating temperature range		 100
VEN ≤ 0.4 V, (LP38693 Only) 0.001 1
IL(MIN) Minimum load current VIN – VO ≤ 4 V
Full operating temperature range		 100
IFB Foldback current limit VIN – VO > 5 V 350 mA
VIN – VO < 4 V 850
PSRR Ripple rejection VIN = VO + 2 V(DC), with 1 V(p-p) / 120-Hz Ripple 55 dB
TSD Thermal shutdown activation (junction temp) 160 °C
TSD (HYST) Thermal shutdown hysteresis (junction temp) 10
en Output noise BW = 10 Hz to 10 kHz
VO = 3.3 V		 0.7 µV/√Hz
VO (LEAK) Output leakage current VO = VO(NOM) + 1 V at 10 VIN 0.5 12 µA
VEN Enable voltage (LP38693 Only) Output = OFF
Full operating temperature range		 0.4 V
Output = ON, VIN = 4 V
Full operating temperature range		 1.8
Output = ON, VIN = 6 V
Full operating temperature range		 3
Output = ON, VIN = 10 V
Full operating temperature range		 4
IEN Enable pin leakage (lLP38693 only) VEN = 0 V or 10 V, VIN = 10 V –1 0.001 1 µA
(1) Typical numbers represent the most likely parametric norm for 25°C operation.
(2) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
(3) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1 mA to full load.
(4) Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100 mV of nominal value.

6.7 Typical Characteristics

Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, EN pin is tied to IN (LP38693 only), VOUT = 1.8 V, VIN = VOUT 1 V, IL = 10 mA.
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126535.png Figure 1. Noise vs Frequency
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126537.png Figure 3. Noise vs Frequency
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126620.gif Figure 5. Ripple Rejection
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126624.gif Figure 7. Line Transient Response
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126528.png Figure 9. Line Transient Response
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126544.png
Figure 11. Load Transient Response
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126531.png Figure 13. VOUT vs Temperature (3.3 V)
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126533.png Figure 15. VOUT vs Temperature (1.8 V)
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126560.png Figure 17. VOUT vs VIN, Power-Up
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126553.png Figure 19. Load Regulation vs Temperature
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126557.gif Figure 21. MIN VIN vs IOUT
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126536.png Figure 2. Noise vs Frequency
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126618.gif Figure 4. Ripple Rejection
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126622.gif Figure 6. Ripple Rejection
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126526.png Figure 8. Line Transient Response
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126542.png Figure 10. Load Transient Response
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126530.png Figure 12. VOUT vs Temperature (5.0 V)
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126532.png Figure 14. VOUT vs Temperature (2.5 V)
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126559.png Figure 16. VOUT vs VIN (1.8 V)
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126552.png Figure 18. Enable Voltage vs Temperature
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126554.png Figure 20. Line Regulation vs Temperature
LP38691 LP38693 LP38691-Q1 LP38693-Q1 20126556.gif Figure 22. Dropout Voltage vs IOUT