LP38690, LP38692 1-A Low Dropout CMOS Linear Regulators Stable with Ceramic Output Capacitors
- SNVS322M December 2004 – December 2015 LP38690 , LP38692
  
  PRODUCTION DATA.

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DATA SHEET

LP38690, LP38692 1-A Low Dropout CMOS Linear Regulators Stable with Ceramic Output Capacitors

1 Features

Wide Input Voltage Range (2.7 V to 10 V)
2.5% Output Accuracy (25°C)
Low Dropout Voltage: 450 mV at 1 A
(typical, 5 V_OUT)
Precision (Trimmed) Bandgap Reference
Ensured Specifications for –40°C to 125°C
1-µA Off-State Quiescent Current
Thermal Overload Protection
Foldback Current Limiting
3-Lead TO-252, 5-Lead SOT-223, and 6-Bump WSON Packages
Enable Pin (LP38692)
Ground Pin Current: 55 µA (typical) at Full Load
Precision Output Voltage: 2.5% (25°C) Accuracy

2 Applications

Hard Disk Drives
Notebook Computers
Battery Powered Devices
Portable Instrumentation

3 Description

The LP38690 and LP38692 low-dropout CMOS linear regulators provide tight output tolerance (2.5% typical), extremely low dropout voltage (450 mV at a 1-A load current, V_OUT = 5 V), and excellent AC performance utilizing ultra low ESR ceramic output capacitors.

The low thermal resistance of the WSON, SOT-223, and TO-252 packages allow the full operating current to be used even in high ambient temperature environments.

The use of a PMOS power transistor means that no DC base drive current is required to bias it allowing ground pin current to remain below 100 µA regardless of load current, input voltage, or operating temperature.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LP38690	TO-252 (3)	6.58 mm x 6.10 mm
LP38690	WSON (6)	3.00 mm x 3.00 mm
LP38692	SOT-223 (5)	6.50 mm x 3.56 mm
LP38692	WSON (6)	3.00 mm x 3.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic for LP38690

* Minimum value required for stability.
**WSON package devices only.

Simplified Schematic for LP38692

* Minimum value required for stability.
**WSON package devices only.

4 Revision History

Changes from L Revision (March 2015) to M Revision

Added top navigator icon for TI Designs Go
Added Caution note to Foldback Current Limiting subsection Go

Changes from K Revision (December 2014) to L Revision

Changed "mA" back to "mV" - error from SDS conversion.Go

Changes from J Revision (April 2013) to K Revision

Changed Device Information and ESD Rating tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; update Thermal Values moved some curves to Application Curves section; change package name PFM to TO-252 (National to TI nomenclature) and pin names from VIN, VOUT to IN, OUT. Go

Changes from I Revision (April 2013) to J Revision

Changed layout of National Data Sheet to TI formatGo

5 Pin Configuration and Functions

LP38690 TO-252 (NDP)

3 Pins

Top View

LP38690 WSON (NGG)

6 Pins

Top View

LP38690/92 SOT-223 (NDC)

5 Pins

Top View

LP38692 WSON (NGG)

6 Pins

Top View

Pin Functions

PIN					TYPE	DESCRIPTION
NAME	LP38690		LP38692
NAME	TO-252	WSON	SOT-223	WSON
EN	—	—	1	3	I	The Enable (EN) pin allows the part to be turned ON and OFF by pulling this pin HIGH or LOW.
GND	TAB	2	5	2	—	Circuit ground for the regulator. For the TO-252 and SOT-223 packages this is thermally connected to the die and functions as a heat sink when soldered down to a large copper plane.
IN	3	1, 6	4	1, 6	I	This is the input supply voltage to the regulator. For WSON devices, both IN pins must be tied together for full current operation (500 mA maximum per pin).
OUT	1	4	3	4	O	Regulated output voltage.
SNS	—	5	—	5	I	WSON only - Output sense pin allows remote sensing at the load which eliminates the error in output voltage due to voltage drops caused by the resistance in the traces between the regulator and the load. This pin must be tied to VOUT.
DAP	—	X	—	X	—	WSON only - The DAP (Exposed Pad) functions as a thermal connection when soldered to a copper plane. See WSON Mounting section in Layout for more information.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
V(max) All pins (with respect to GND)	–0.3	12	V
I_OUT⁽³⁾	Internally limited
Junction temperature	−40	150	°C
Lead temperature (soldering, 5 seconds)		260	°C
Power dissipation⁽²⁾	Internally limited
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used). When using the WSON package, refer to TI Application Report AN-1187 Leadless Leadframe Package (LLP) (SNOA401) and the WSON Mounting section in this datasheet. If power dissipation causes the junction temperature to exceed specified limits, the device goes into thermal shutdown.

(3) If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_IN supply voltage		2.7		10	V
Operating junction temperature		−40		125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LP38690	LP38690/92	LP38692	UNIT
		TO-252	WSON	SOT-223
		3 PINS	6 PINS	5 PINS
R_θJA⁽²⁾	Junction-to-ambient thermal resistance	50.5	50.6	68.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	52.6	44.4	52.2	°C/W
R_θJB	Junction-to-board thermal resistance	29.7	24.9	13.0	°C/W
ψ_JT	Junction-to-top characterization parameter	4.8	0.4	5.5	°C/W
ψ_JB	Junction-to-board characterization parameter	29.3	25.1	12.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.5	5.4	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) Junction-to-ambient thermal resistance, High-K.

6.5 Electrical Characteristics

Unless otherwise specified: V_IN = V_OUT + 1 V, C_IN = C_OUT = 10 µF, I_LOAD = 10 mA, and limits are for T_J = 25°C. Minimum (MIN) and maximum (MAX) limits are specified through testing, statistical correlation, or design.

PARAMETER		TEST CONDITIONS		MIN	TYP⁽¹⁾	MAX	UNIT
V_OUT	Output voltage tolerance			–2.5		2.5	%V_OUT
V_OUT	Output voltage tolerance	100 µA < I_L < 1 A V_O + 1 V ≤ V_IN ≤ 10 V −40°C ≤ T_J ≤ 125°C		–5		5	%V_OUT
ΔV_OUT/ΔV_IN	Output voltage line regulation⁽²⁾	V_OUT + 0.5 V ≤ V_IN ≤ 10 V I_L = 25 mA			0.03		%/A
ΔV_OUT/ΔV_IN	Output voltage line regulation⁽²⁾	V_OUT + 0.5 V ≤ V_IN ≤ 10 V I_L = 25 mA −40°C ≤ T_J ≤ 125°C				1	%/A
ΔV_OUT/ΔI_L	Output voltage load regulation⁽³⁾	1 mA < I_L < 1 A V_IN = V_OUT + 1 V			1.8		V
ΔV_OUT/ΔI_L	Output voltage load regulation⁽³⁾	1 mA < I_L < 1 A V_IN = V_OUT + 1 V −40°C ≤ T_J ≤ 125°C				5	V
V_IN – V_OUT	Dropout voltage⁽⁴⁾	V_OUT = 1.8 V I_L = 1 A			950		mV
		V_OUT = 1.8 V I_L = 1 A −40°C ≤ T_J ≤ 125°C				1600
		V_OUT = 2.5 V	I_L = 0.1 A		80
		V_OUT = 2.5 V	I_L = 1 A		800
		V_OUT = 2.5 V −40°C ≤ T_J ≤ 125°C	I_L = 0.1 A			145
		V_OUT = 2.5 V −40°C ≤ T_J ≤ 125°C	I_L = 1 A			1300
		V_OUT = 3.3 V	I_L = 0.1 A		65
		V_OUT = 3.3 V	I_L = 1 A		650
		V_OUT = 3.3 V −40°C ≤ T_J ≤ 125°C	I_L = 0.1 A			110
		V_OUT = 3.3 V −40°C ≤ T_J ≤ 125°C	I_L = 1 A			1000
		V_OUT = 5 V	I_L = 0.1 A		45
		V_OUT = 5 V	I_L = 1 A		450
		V_OUT = 5 V, −40°C ≤ T_J ≤ 125°C	I_L = 0.1 A			100
		V_OUT = 5 V, −40°C ≤ T_J ≤ 125°C	I_L = 1 A			800
I_Q	Quiescent current	V_IN ≤ 10 V, I_L = 100 µA to 1 A			55		µA
		V_IN ≤ 10 V, I_L = 100 µA to 1 A −40°C ≤ T_J ≤ 125°C				100
		V_EN ≤ 0.4 V (LP38692 only)			0.001
I_L(MIN)	Minimum load current	V_IN – V_OUT ≤ 4 V −40°C ≤ T_J ≤ 125°C				100
I_FB	Foldback current limit	V_IN – V_OUT > 5 V			450		mA
I_FB	Foldback current limit	V_IN – V_OUT < 4 V			1500		mA
PSRR	Ripple rejection	V_IN = V_OUT + 2 V_(DC), with 1V_(p-p) / 120 Hz ripple			55		dB
T_SD	Thermal shutdown activation (junction temp)				160		°C
T_SD (HYST)	Thermal shutdown hysteresis (junction temp)				10		°C
e_n	Output noise	V_OUT = 3.3 V, BW = 10 Hz to 10 kHz			0.7		µV/√Hz
V_OUT (LEAK)	Output leakage current	V_OUT = V_OUT(NOM) + 1 V at 10 V_IN			0.5	12	µA
V_EN	Enable voltage (LP38692 only)	Output = OFF, −40°C ≤ T_J ≤ 125°C				0.4	V
		Output = ON, V_IN = 4 V −40°C ≤ T_J ≤ 125°C		1.8
		Output = ON, V_IN = 6 V −40°C ≤ T_J ≤ 125°C		3
		Output = ON, V_IN = 10 V −40°C ≤ T_J ≤ 125°C		4
I_EN	Enable pin leakage	V_EN = 0 V or 10 V, V_IN = 10 V		–1	0.001	1	µA

(1) Typical numbers represent the most likely parametric norm for 25°C operation.

(2) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

(3) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1 mA to full load.

(4) Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100 mV of nominal value.

6.6 Typical Characteristics

Unless otherwise specified: T_J = 25°C, C_IN = C_OUT = 10 µF, EN pin is tied to V_IN (LP38692 only), V_OUT = 1.8 V, V_IN = V_OUT + 1 V, I_L = 10 mA.

Figure 1. Noise vs Frequency

Figure 3. Noise vs Frequency

Figure 2. Noise vs Frequency

Figure 4. Ripple Rejection

Figure 5. Ripple Rejection

Figure 7. Line Transient Response

Figure 9. Line Transient Response

Figure 11. Load Transient Response

Figure 13. Load Transient Response

Figure 15. V_OUT vs Temperature (5 V)

Figure 17. V_OUT vs Temperature (2.5 V)

Figure 19. V_OUT vs V_IN (1.8 V)

Figure 21. Dropout Voltage vs I_OUT

Figure 23. Enable Voltage vs Temperature

Figure 25. Line Regulation vs Temperature

Figure 6. Ripple Rejection

Figure 8. Line Transient Response

Figure 10. Load Transient Response

Figure 12. Load Transient Response

Figure 14. Load Transient Response

Figure 16. V_OUT vs Temperature (3.3 V)

Figure 18. V_OUT vs Temperature (1.8 V)

Figure 20. V_OUT vs V_IN (Power-Up)

Figure 22. Dropout Voltage vs I_OUT

Figure 24. Load Regulation vs Temperature

7 Detailed Description

7.1 Overview

The LP38690 and LP38692 devices are designed to meet the requirements of portable, battery-powered digital systems providing an accurate output voltage with fast start-up. When disabled via a low logic signal at the enable pin (EN), the power consumption is reduced to virtually zero (LP38692 only). The LP38690 and LP38692 perform well with a single 1-μF input capacitor and a single 1-μF ceramic output capacitor.

7.2 Functional Block Diagrams

Figure 26. LP38690 Functional Diagram (TO-252)

Figure 27. LP38690 Functional Diagram (WSON)

Figure 28. LP38692 Functional Diagram (SOT-223)

Figure 29. LP38692 Functional Diagram (WSON)

7.3 Feature Description

7.3.1 Enable (EN)

The LP38692 has an Enable pin (EN) which allows an external control signal to turn the regulator output On and Off. The Enable On/Off threshold has no hysteresis. The voltage signal must rise and fall cleanly, and promptly, through the ON and OFF voltage thresholds. The EN pin voltage must be higher than the V_EN(MIN) threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the V_EN(MAX) threshold to ensure that the device is fully disabled. The Enable pin has no internal pull-up or pull-down to establish a default condition and, as a result, this pin must be terminated either actively or passively. If the Enable pin is driven from a source that actively pulls high and low, the drive voltage should not be allowed to go below ground potential or higher than V_IN. If the application does not require the Enable function, the pin should be connected directly to the IN pin.

7.3.2 Thermal Shutdown Protection (TSD)

Thermal shutdown disables the output when the junction temperature rises to approximately 160°C which allows the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry enables.

Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.

The TSD circuitry of the LP38692 has been designed to protect against temporary thermal overload conditions. The TSD circuitry was not intended to replace proper heat-sinking. Continuously running the LP38692 device into thermal shutdown degrades device reliability.

7.3.3 Foldback Current Limiting

Foldback current limiting is built into the LP38690 and LP38692 which reduces the amount of output current the part can deliver as the output voltage is reduced. The amount of load current is dependent on the differential voltage between V_IN and V_OUT. Typically, when this differential voltage exceeds 5 V, the load current limits at about 450 mA. When the V_IN – V_OUT differential is reduced below 4 V, load current is limited to about 1500 mA.

CAUTION

When toggling the LP38692 Enable (EN) after the input voltage (V_IN) is applied, the foldback current limit circuitry is functional the first time that the EN pin is taken high. The foldback current limit circuitry is non-functional the second, and subsequent, times that the EN pin is taken high. Depending on the input and output capacitance values the input inrush current may be higher than expected which can cause the input voltage to droop.

If the EN pin is connected to the IN pin, the foldback current limit circuitry is functional when V_IN is applied if V_IN starts from less than 0.4 V.

7.4 Device Functional Modes

7.4.1 Enable (EN)

The EN pin voltage must be higher than the V_EN(MIN) threshold to ensure that the device is fully enabled under all operating conditions.

7.4.2 Minimum Operating Input Voltage (V_IN)

The LP38690 and LP38692 devices do not include any dedicated UVLO circuitry. The LP38690 and LP38692 internal circuitry is not fully functional until V_IN is at least 2.7 V. The output voltage is not regulated until V_IN ≥ (V_OUT + V_DO), or 2.7 V, whichever is higher.