7.3.1 Undervoltage Lockout (UVLO)

The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is below the UVLO threshold of approximately 2.45 V.

As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.

When the bias voltage is between the UVLO threshold and the minimum operating rating value of 3 V the device is functional, but the operating parameters are not within the specified limits.

7.3.2 Supply Sequencing

There is no requirement for the order that V_IN or V_BIAS are applied or removed.

One practical limitation is that the soft-start circuit starts charging soft-start timing capacitor (C_SS) when both V_BIAS rises above the UVLO threshold and the EN pin is above the V_EN(ON) threshold. If the application of V_IN is delayed beyond this point the benefits of soft start is compromised.

In any case, the output voltage cannot be ensured until both V_IN and V_BIAS are within the range of specified operating values.

If used in a dual-supply system where the regulator output load is returned to a negative supply, the OUT pin must be diode clamped to ground. A Schottky diode is recommended for this diode clamp.

7.3.3 Reverse Voltage

A reverse voltage condition exists when the voltage at the OUT pin is higher than the voltage at the IN pin. Typically this happens when V_IN is abruptly taken low, and C_OUT continues to hold a sufficient charge such that the input to output voltage becomes reversed.

The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass element is not driven, there is no reverse current flow through the pass element during a reverse voltage event. The gate of the pass element is not driven when V_BIAS is below the UVLO threshold, or when the EN pin is held low.

When V_BIAS is above the UVLO threshold, and the EN pin is above the V_EN(ON) threshold, the control circuitry is active and attempts to regulate the output voltage. Because the input voltage is less than the output voltage the control circuit drives the gate of the pass element to the full V_BIAS potential when the output voltage begins to fall. In this condition, reverse current flows from the OUT pin to the IN pin , limited only by the R_DS(ON) of the pass element and the output-to-input voltage differential. Discharging an output capacitor up 1000 µF in this manner does not damage the device as the current rapidly decays. However, continuous reverse current must be avoided.

7.3.4 Soft-Start

The LP38852-ADJ incorporates a soft-start function that reduces the start-up current surge into the output capacitor (C_OUT) by allowing V_OUT to rise slowly to the final value. This is accomplished by controlling V_REF at the SS pin. C_SS is internally held to ground until both V_BIAS rises above the UVLO threshold and the EN pin is higher than the V_EN(ON) threshold.

V_REF rises at an RC rate defined by the internal resistance of the SS pin (r_SS) and the external capacitor connected to the SS pin. This allows the output voltage to rise in a controlled manner until steady-state regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is sufficiently close to the final steady-state value. During the soft-start time the output current can rise to the built-in current limit.

Because the V_OUT rise is exponential, not linear, the in-rush current peaks during the first time constant (τ), and V_OUT requires four additional time constants (4τ) to reach the final value (5τ) .

After achieving normal operation, if either V_BIAS falls below the ULVO threshold, or the EN pin falls below the V_EN(OFF) threshold, the device output is disabled, and the C_SS discharge circuit becomes active. The C_SS discharge circuit remains active until V_BIAS falls to 500 mV (typical). When V_BIAS falls below 500 mV (typical), the C_SS discharge circuit ceases to function due to a lack of sufficient biasing to the control circuitry.

Because V_REF appears on the SS pin, any leakage through C_SS causes V_REF to fall, thus affecting V_OUT. A leakage of 50 nA (about 10 MΩ) through C_SS causes V_OUT to be approximately 0.1% lower than nominal, while a leakage of 500 nA (about 1 MΩ) causes V_OUT to be approximately 1% lower than nominal. Typical ceramic capacitors have a factor of 10× difference in leakage between 25°C and 85°C, so the maximum ambient temperature must be included in the capacitor selection process.

Typical C_SS values are in the range of 1 nF to 100 nF, providing typical soft-start times in the range of 70 μs to 7 ms (5τ). Values less than 1 nF may be used, but the soft-start effect is minimal. Values larger than 100 nF provide soft start but may not be fully discharged if V_BIAS falls from the UVLVO threshold to less than 500 mV in less than 100 µs.

Figure 22 shows the relationship between the C_OUT value and a typical C_SS value.

Figure 22. Typical C_SS vs C_OUT Values

The C_SS capacitor must be connected to a clean ground path back to the device ground pin. No components, other than C_SS, should be connected to the SS pin, as there could be adverse effects to V_OUT.

If the soft-start function is not needed the SS pin must be left open, although some minimal capacitance value is always recommended.

7.3.5 Setting The Output Voltage

The output voltage is set using the external resistive divider R1 and R2. (Refer to the Figure 23.) The output voltage is given by Equation 2:

Equation 2.

The resistors used for R1 and R2 must be high quality, tight tolerance, and with matching temperature coefficients. It is important to remember that, although the value of V_ADJ is specified, the use of low quality resistors for R1 and R2 can easily produce a V_OUT value that is unacceptable.

It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the F_Z pole set by R1 and C_FF.

Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10% capacitor values for C_FF, for a range of V_OUT values. Other values of R1, R2, and C_FF are available that give similar results.

Please refer to the TI Application Note AN-1378 Method for Calculating Output Voltage Tolerances in Adjustable Regulators (SNVA112) for additional information on how resistor tolerances affect the calculated V_OUT value.

7.3.6 Enable (EN)

The EN pin provides a mechanism to enable, or disable, the regulator output stage. The EN pin has an internal pullup to V_BIAS through a 180-kΩ (typical) resistor. The EN pin can be left open or connected V_BIAS if the enable function is not needed.

7.4.1 Input Voltage

The input voltage (V_IN) is the high-current external voltage rail that is regulated down to a lower voltage, which is applied to the load. The input voltage must be at least V_OUT + V_DO and no higher than whatever value is used for V_BIAS.

For applications where V_BIAS is higher than 4.5 V, V_IN must be no greater than 4.5 V, otherwise output voltage accuracy may be affected.

7.4.2 Bias Voltage

The bias voltage (V_BIAS) is a low-current external voltage rail required to bias the control circuitry and provide gate drive for the N-FET pass transistor. When V_OUT is set to 1.2 V, or less, V_BIAS may be anywhere in the operating range of 3 V to 5.5 V. If V_OUT is set higher than 1.2 V , V_BIAS must be between 4.5 V and 5.5 V to ensure proper operation of the device.

7.4.3 Enable (EN) Operation

If the EN pin is actively driven, pulling the EN pin above the V_EN threshold of 1.25 V (typical) turns on the regulator output; pulling the EN pin below the V_EN threshold turns off the regulator output. There is approximately 100 mV of hysteresis built into the enable threshold provide noise immunity.

If the enable function is not needed the EN pin must be left open, or connected directly to V_BIAS. If the EN pin is left open, stray capacitance on this pin must be minimized; otherwise, the output turnon is delayed while the stray capacitance is charged through the internal resistance (r_EN).