SNVS482F January   2007  – December 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO)
      2. 7.3.2 Supply Sequencing
      3. 7.3.3 Reverse Voltage
      4. 7.3.4 Soft-Start
      5. 7.3.5 Setting The Output Voltage
      6. 7.3.6 Enable (EN)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Voltage
      2. 7.4.2 Bias Voltage
      3. 7.4.3 Enable (EN) Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Input Capacitor
          2. 8.2.2.1.2 Output Capacitor
          3. 8.2.2.1.3 Bias Capacitor
          4. 8.2.2.1.4 Setting the Output Voltage
          5. 8.2.2.1.5 Feed Forward Capacitor, CFF
        2. 8.2.2.2 Power Dissipation and Heat Sinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near to the respective LDO pin connections as practical. Place ground return connections to the input and output capacitor, and to the LDO ground pin, as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitic, and thereby reduces load current transients, minimizes noise, and increases circuit stability.

A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and it behaves similarly to a thermal plane to spread heat from the LDO device when connected to the SO PowerPAD. In most application, this ground plane is necessary to meet thermal requirements.

10.2 Layout Examples

LP38852-ADJ 7-pinlayout_snvs482.gif Figure 31. LP38852 DDPAK/TO-263 and TO-220 Layout Example
LP38852-ADJ 8-pinlayout_snvs482.gif Figure 32. LP38852 SO PowerPAD Layout Example