SNVS336F June   2006  – August 2015 LP38856

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable Operation
      2. 7.3.2 Input Voltage
      3. 7.3.3 Bias Voltage
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Supply Sequencing
      6. 7.3.6 Reverse Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with 3 V ≤ VBIAS ≤ 5.5 V , VOUT(TARGET) + 0.3 V ≤ VIN ≤ VBIAS
      2. 7.4.2 Operation with VEN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Output Capacitor
          2. 8.2.2.1.2 Input Capacitor
          3. 8.2.2.1.3 Bias Capacitor
        2. 8.2.2.2 Power Dissipation and Heatsinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP38856 can provide 3-A output current with 240-mV dropout voltage (typical). The bias voltage must be in the range of 3 V to 5.5 V to ensure proper operation of the device. The input voltage must be at least VOUT + VDO, and no higher than whatever value is used for VBIAS. Minimal input and output capacitor are 10 µF. The capacitor on the bias pin must be at least 1 μF.

8.2 Typical Application

LP38856 20131101.gifFigure 23. LP38856 Typical Application

8.2.1 Design Requirements

For LP38856 typical applications, use the parameters listed in Table 1 as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETERS VALUE
Bias voltage 3 V to 5.5 V
Input voltage VOUT+0.3 V to VBIAS
Output voltage 0.8 V or 1.2 V
Output current 3 A (maximum)
Bias capacitor 1 µF (minimum)
Input capacitor 10 µF (minimum)
Output capacitor 10 uF (minimum)

8.2.2 Detailed Design Procedure

8.2.2.1 External Capacitors

To assure regulator stability, capacitors are required on the IN, OUT, and BIAS pins as shown in Figure 23.

8.2.2.1.1 Output Capacitor

A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the device and returned to the device ground pin with a clean analog ground.

Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide sufficient capacitance over temperature.

Tantalum capacitors will also provide stable operation across the entire operating temperature range. However, the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum recommended 10 µF ceramic capacitor at the output will allow unlimited capacitance, tantalum and/or aluminum, to be added in parallel.

8.2.2.1.2 Input Capacitor

The input capacitor must be at least 10 µF, but can be increased without limit. Its purpose is to provide a low source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended.

Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor (the lower, the better).

Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at cold temperatures. They are not recommended for any application where the ambient temperature falls below 0°C.

8.2.2.1.3 Bias Capacitor

The capacitor on the bias pin must be at least 1 µF. It can be any good quality capacitor (ceramic is recommended).

8.2.2.2 Power Dissipation and Heatsinking

A heat-sink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions.

The total power dissipation of the device is the sum of three different points of dissipation in the device.

The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula:

Equation 1. PD(PASS) = (VIN - VOUT) × IOUT

The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the formula:

Equation 2. PD(BIAS) = VBIAS × IGND(BIAS)

where

  • IGND(BIAS) is the portion of the operating ground current of the device that is related to VBIAS.

The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with the formula:

Equation 3. PD(IN) = VIN × IGND(IN)

where

  • IGND(IN) is the portion of the operating ground current of the device that is related to VIN.

The total power dissipation is then:

Equation 4. PD = PD(PASS) + PD(BIAS) + PD(IN)

The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient temperature (TA(MAX)) for the application, and the maximum allowable operating junction temperature (TJ(MAX)):

Equation 5. ΔTJ = TJ(MAX) – TA(MAX)

The maximum allowable value for junction to ambient thermal resistance, RθJA, can be calculated using the formula:

Equation 6. RθJA ≤ ΔTJ / PD

The LP38856 is available in TO-220 and DDPAK/TO-263 packages. The thermal resistance in the application depends on amount of copper area or heat-sink, and on air flow. If the maximum allowable value of R θJA calculated above is ≥ 32°C/W for TO-220 package and ≥ 41°C/W for DDPAK/TO-263 package no heat-sink is needed because the package alone can dissipate enough heat to satisfy these requirements. If the value needed for allowable RθJA falls below these limits, a heat-sink is required.

8.2.3 Application Curves

LP38856 20131178.png
Figure 24. VIN Line Transient Response
LP38856 20131182.png
COUT = 10-μF Ceramic
Figure 25. Load Transient Response