8.3.3 Flexible Power-On Reset (Power Good with Delay)

The LP3907 is equipped with an internal power-on-reset (POR) circuit which monitors the output voltage levels on Bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck outputs are below 91% of the rising value, or when one or both outputs fall below 82% of the desired value. The time delay between output voltage level and nPOR is enabled is (50 µs, 50 ms, 100 ms, 200 ms) 50 ms by default. The system designer can choose the external pullup resistor (that is, 100 kΩ) for the nPOR pin.

Figure 35. nPOR with Counter Delay

Figure 35 shows the simplest application of the POR, where both switcher enables are tied together. In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power supply for Buck2 does not come on within that period, nPOR stays LOW, indicating a power fail mode. Case 2 indicates the vice versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW.

Case 3 shows a typical application of the POR, where both switcher enables are tied together. Even if RDY1 ramps up slightly faster than RDY2 (or vice versa), then nPOR signal triggers a programmable delay before going HIGH, as explained below.

Figure 36. Faults Occurring in Counter Delay After Start-Up

Figure 36 details the power good with delay with respect to the enable signals EN1, and EN2. The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has been trimmed as follows:

The circuits for EN1 and RDY1 is symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 also works for EN2 and RDY2 and vice versa.

If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay counter (50 μs, 50 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. nPOR is then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this interval the nPOR signal ignores this event.

If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again.

Figure 37. nPOR Mask Window

If the EN1 and RDY1 are initiated in normal operation, then nPOR is asserted and deasserted as explained in Figure 37.

Case 1 shows the case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent the nPOR being asserted again, a masked window (5 ms) counter delay is triggered off the EN2 rising edge. nPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards depends on the status of both RDY1 and RDY2 lines.

Case 2 shows the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2 never goes HIGH (Buck2 never turns on). Normal operation operation of nPOR occurs wilth respect to EN1 and RDY1, and the nPOR signal is held HIGH for the duration of the mask window. We see that nPOR goes LOW after the masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW.

Figure 38. Design Implementation of the Flexible Power-On Reset

An internal power-on reset of the device is used with EN1, and EN2 to produce a reset signal (LOW) to the delay timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer. S = R = 1 never occurs. The mask timers are triggered off EN1 and EN2 which are gated with RDY1, and RDY2 to generate outputs to the final AND gate to generate the nPOR.