Table 4. Supply Specification

8.3.1.1 Buck1, Buck2 Operation

Buck1 is recommended to be used as the processor core supply and has I²C selectable output voltages ranging from 0.8 V to 2 V (typical). Buck2 is recommended for I/O power, Memory power and logic power. Its voltage range can be programmed using the I²C interface from 1.8 V to 3.3 V (typical). The default output voltage for each buck converter is factory programmable (see Application and Implementation).

The system designer can also determine the output voltage of either Buck1 or Buck2 through an external feedback resistor ladder by clearing the output voltage selection field in the Buck1 or Buck2 control registers.

Figure 49. External Control Of Buck Output Voltage Through Feedback Resistor Ladder

8.3.1.2 Circuit Operation Description

A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of V_IN – V_OUT / L.

by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of –V_OUT / L.

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load.

8.3.1.3 PWM Operation

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed-forward voltage inversely proportional to the input voltage is introduced.

8.3.1.4 Internal Synchronous Rectification

While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode.

8.3.1.5 Current Limiting

A current limit feature allows the buck to protect itself and external components during overload conditions PWM mode implements cycle-by-cycle current limiting using an internal comparator that trips at 1000 mA (typical).

8.3.1.6 PFM Operation

At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency.

The device automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles:

The inductor current becomes discontinuous or the peak PMOS switch current drops below the I_MODE level:

Equation 1.

During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the high PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the high PFM threshold or the peak current exceeds the I_PFM level set for PFM mode. The typical peak current in PFM mode is:

Equation 2.

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the high PFM comparator threshold (see Figure 50), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this sleep mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the low PFM threshold, the cycle repeats to restore the output voltage to approximately 1.6% above the nominal PWM output voltage.

If the load current increases during PFM mode (see Figure 50) causing the output voltage to fall below the ‘low2’ PFM threshold, the device automatically transitions into fixed-frequency PWM mode.

Figure 50. Operation in PFM Mode and Transfer to PWM Mode

8.3.3.1 No-Load Stability

The LDOs remain stable and in regulation with no external load. This is an important consideration in some circuits, for example, CMOS RAM keep-alive applications.

8.3.4.1 Charger Architecture

The LP3910 can safely charge and maintain a single cell Li-ion or Li-polymer battery operating from a regulated 6-V car adapter, AC wall adapter, or USB power (VBUS). Input power source selection of USB/adapter is seamless. If present, the charger uses the adapter power regardless of the presence of USB power. The connection of either power source is detected by the LP3910 device.

Figure 53. Charger Architecture

The charger module is a linear charger with constant current pre-qualification, CC full-rate charging and CV charging. CC and CV regulation is performed using an internal Power FET Q2 with reverse current blocking. The termination voltage is controlled to within ±0.35% at room temperature.

The power FET Q1 acts as a switch with programmable current limit for USB operation.

Figure 54. Switches for USB Charging Path

8.3.4.2 Charge Status Indication

Two LEDs connected to the LP3910 are used to indicate the status of the charging. The CHG pin is connected to a red LED that is enabled when an external power source is connected and the battery is charging. The second STAT pin is connected to a green LED. When the battery charging transitions from CC to CV mode, then the green LED is blinking with a 50% duty cycle and a period of 1 second. When the battery is fully charged, then the green LED is always on.

Both LEDs are off when there is no external power connected.

50% duty cycle indicates the LED is pulsed on and off for equal times at a frequency of 1 Hz.

The RED pin and GREEN pin are connected to a regulated driver to ensure that the brightness is independent from the external power. The LEDs need to be connected between the CHG and STAT pins and GND.

8.3.4.3 Thermal Charger Power FET Regulation

The internal power FET Q2 in the linear charger module is thermally regulated to the junction temperature of 115°C to ensure optimal charging of the battery. The charge current is limited by the charge current selected in the charger control register but is also thermally limited to prevent the junction from overheating during high charge currents at high ambient temperatures as the package power dissipation is limited.

Thermal regulation ensures maximum charge current and superior charge rate without exceeding the power dissipation limits of LP3910 device.

8.3.4.4 Battery Charger Operating Modes

8.3.4.4.5 Charge Cycle Complete

During charge cycle complete, the charger is automatically disabled, regardless of the state of the charge enable bit. In charge cycle complete, the STAT2, STAT1 and STAT0 bits are respectively logic 1, logic 0, and logic 1. When the battery voltage drops below the V_RESTART threshold, charging resumes in full-rate charging mode.

Figure 55. Charge Cycle Complete

8.3.4.5 Battery Temperature Monitoring (TS Pin)

The LP3910 is equipped with a battery thermistor terminal to continuously monitor the battery temperature by measuring the voltage between the T_S pin and GND. With the T_S pin connected to the battery thermistor, charging is allowed only if the battery temperature is within the acceptable temperature range set by a pair of internal comparators inside the LP3910. The temperature window is 0°C to 45°C or 0°C to 50°C, depending on the setting of D2 of the charger supervisory (CHSPV) register. There is 3°C of temperature hysteresis associated with each temperature threshold. The default temperature range is 0°C to 50°C and can be changed to 0°C to 45°C by setting bit D3 in the CHSPV register. If the battery temperature is out of range, STAT2, STAT1, and STAT0 bits in the CHSPV register are set to logic1, logic0, logic0, and charging is suspended.

The TS pin is only active during charging and draws no current from the battery when no external power source is present.

If the TS pin is not used in the application, it must be connected to GND through a 100-kΩ pulldown resistor.

When the TS pin is left floating (battery removal), the charger is disabled as the TS voltage exceeds the lower temperature limit.

Figure 56. Battery Temperature Monitor with TS Pin

8.3.4.6 Disabling Charger

Charging can be safely interrupted by clearing the Charge enable bit D1 in the Charge Control Register and can subsequently resume upon setting this bit. When the charger is disabled, STAT2, STAT1, and STAT0 bits in the CHSPV register are set to logic 0.

8.3.4.7 Safety Timer

In order to prevent endless charging, which could degrade the battery quality and life time, the LP3910 contains a safety timer that limits charging regardless whether the battery has reached its full capacity or not. In prequalification the safety timer is 1 hour. In full rate or constant voltage charging the safety timer is a maximum of 10 hours minus the time in prequalification.

When the timer times out of uninterrupted charging, an IRQ is generated to alert system processor. The status of the timer can also be polled by reading the IRQ register if the system doesn’t support hardware interrupts.

The safety timer resets and starts counting from zero upon the following events:

1. Power ON (through connecting valid power to either USBPWR or CHGN_IN pins).
2. Interchanging USBPWR and CHG_IN sources.
3. The voltage of a charged battery drops below the restart value, and the charger is enabled.
4. Disabling and re-enabling of the charger by toggling bit D1 of the Charge Control Register.
5. Emerging from thermal shutdown.
6. Emerging from a battery temperature out-of-range, and the charger is enabled.
7. Emerging from USB suspend mode when charging with USB power.

8.3.4.8 Charging Maintenance

When a fully charged battery is being loaded by the system while the external power is present and while bit D1 in the charge control register is set to a 1 (charge enable) then the charging restarts when the battery voltage drops below the charging restart threshold. The value of the threshold depends on the termination voltage according to the following table:

8.3.5.1 Battery Voltage Measurement

The battery voltage scalar transforms the battery voltage ranging from 2.6 V to 3.5 V to the reference voltage interval: [V_REFH, 2*V_REFH]. A wider voltage range (2.6 V to 4.4 V) can be selected through I²C by setting the voltage range bit D7 in register 0xA to 0’b1.

8.3.5.2 Battery Charge Current Measurement

The battery charge current is indirectly measured by measuring the voltage across the ISENSE resistor, R_SENSE. A fixed portion of the battery charge current is mirrored over the R_SENSE as in Equation 3:

where K is a ratio between the I_SENSE current and the charge current.

The battery charge current scalar transforms the voltage across the external ISENSE resistor to the [V_REFH, 2 × V_REFH] input voltage interval of the ADC.

Figure 58. Battery Charge Scalar

8.3.5.3 External General-Purpose Sources

Two additional ADC sources are available on the ADC1 and ADC2 pins of the LP3910. These two external ADC sources are not internally scaled and have an input voltage range of [V_REFH, 2 × V_REFH]. The system designer can use these two sources for general-purpose applications such as resistive keyboard matrix scanning, temperature measurements, battery load current, battery ID resistor measurement, and others.

Figure 59. ADC Analog Front-End Block Diagram

The source selection and the access to the conversion results are established through the I²C linked control registers: ADCC and ADCD.

The ADC is by default disabled to minimize current consumption and must be enabled by setting D2 in the ADCC register. Writing a logic 1 to bit D3 in the ADC initiates a conversion. It is advised to select the correct ADC source before a conversion is started. The ADC sets bit D4 in the ADCC register upon the completion of a conversion, which is typically 4 ms after the start of the conversion. At the same time an interrupt request is generated. (See IRQ Register (0d)H Interrupt Request Register).

To save power, disable the ADC by setting bit 2 of D2 to 0. To make repetitive starts, set bit D3 to 0 then to 1 for register 0Ah to initiate start of conversion. The interrupt driven protocol between LP3910 and the system processor is the most efficient way to acquire data from successive measurements as shown in Figure 60:

Figure 60. Data Measurement and Acquisition Sequence

8.3.6.1 Interrupts and Standby Mode

Interrupts are captured in standby mode and can be serviced when the system processor is enabled when the LP3910 is in an active state.

8.3.6.2 Interrupt Sources

• CHG_IN Power Detected and CHG_IN Disconnect (INT0 and INT1): An interrupt (INT0) is generated when CHG_IN power is connected to the LP3910. Another interrupt (INT1) is generated upon CHG_IN power removal.
• USB Power Detected and USB Disconnect (INT2 and INT3): An interrupt (INT2) is generated when USB power is connected to the LP3910. Another interrupt (INT3) is generated upon disconnecting the USB power.
• Battery Low (INT4): When the battery voltage drops below the battery low threshold IRQ, an interrupt is generated. This allows the processor to perform some routine tasks prior to going to standby mode.
• Thermal Alarm (INT5): If the junction temperature of the LP3910 exceeds 115°C, an interrupt is generated.
• ADC Conversion Done (INT6): The ADC generates an interrupt request upon the completion of a data conversion.
• Charger Timer Interrupt (INT7): A charger timeout occurs 10 hours after it started (see Li-Ion Linear Charger) and subsequently requests an interrupt.

Table 7. Power Routing Options

Table 8. Power State Table

8.4.1.1 Power-Off Mode

In power-off mode the main battery, the battery charger supply, and the USB supply are below their minimum on levels. All internal circuits are disabled as the supply voltage is below the level to activate them. The LP3910 is in power-off mode when the battery voltage is below the battery V_UVLO (2.4 V, typical) except when a valid external supply is detected.

8.4.1.2 Standby Mode

When the LP3910 is in standby mode, the chip is waiting for a valid power-on event to transition to active mode. There are 3 valid wake-up signals. First is the ONOFF pin. Second is wall adapter insertion. Third is the USB insertion. V_BATT must be greater than the battery V_UVLO in order to stay in standby mode; otherwise, the chip transitions to power-off mode. Standby mode is skipped when advancing from power-off mode when a battery is inserted that is above the battery low alarm threshold.

If the battery is below the battery low alarm threshold, power-off mode transitions to standby mode. However, hot insertion of the battery with the adapter connected is NOT permitted. In standby mode, the current consumption is reduced to I_Q (10 µA, typical).

8.4.1.3 Active Mode

All LP3910 circuits are fully operational in active mode.

8.4.2.1 Power-On, Power-Off Sequencing

Each DC-DC converter (Buck1, Buck2, Buck-Boost, LDO1, LDO2) and the NRST pin of the LP3910 has its own delay after which it is enabled following a power-on event or disabled following a power-off event. Following the deglitching of the power-on event, the system bandgaps are enabled. Following this is a 5 ms delay that internal circuitry requires to cleanly power up. The programmable delays are measured from this time point. Following the deglitching of a power-down event (up to 5 ms if POWERACK pin is used), the power-down sequencer starts. Each delay ranges from 0 ms to 63 ms in steps of 1 ms and is factory programmed to the desired values submitted by the system designer. As shown in Figure 66, the power-on or power-off sequencing is designed around a 6-bit up or down timer that is clocked at 1 kHz. A power-on or power-off event triggers the timer, which counts up from 0 during a power-on sequence and counts down from 5'b11111 during a power-down cycle. The timer output is connected to 5 comparators with factory-programmed timeout values that correspond to the on and off delays for each DC-DC converter and the NRST pin. Once the timer has incremented beyond the comparator timeout value during a power-on cycle, the output of the comparator enables the corresponding DC-DC converter or raises the NRST pin to a logic high level. Subsequently, once the timer has decremented below the comparator timeout value during a power-down cycle, the output of the comparator disables the corresponding DC-DC converter or activates the NRST pin to a logic low level.

Figure 66. Power Sequencer Block Diagram

8.4.2.2 Power-On Timing

Each timeout T1 thru to T5 are factory programmed from 0 ms to 63 ms. The power-on defaults are shown in Table 9.

8.4.2.3 Power-Off Timing

The timing delays during a power-off sequence are equal to 63 ms minus the timing delay during the power on sequence (see Table 10).

8.4.2.4 Transitioning From Standby to Active Mode (Power Up) Battery Power Present Only

When only battery power is present and the battery voltage V_BATT > V_BATTLOW, the LP3910 is waiting for one of three valid wakeup signals. The first is the ONOFF pin. The second and third wakeups are the wall adapter and USBPWR. The ONOFF pin is a factory-programmable wakeup source. It can be a rising edge, a falling edge, a level high, or a level low event. Regardless of the mode, the signal requires a 32-ms deglitch time. A deglitched version of the ONOFF pin is output on the open-drain output pin ONSTAT. ONOFF is usually connected to a push button. Asserting the ONOFF pin starts the power-on sequencer. This enables the DC-DC converters, including the Buck1 DC-DC converter that supplies power to the system processor. The system processor then must set bit D4 (PACK bit) in the power-on event register through the I²C interface or apply a logic high to the POWERACK pin to keep the device in the Active mode. These serve as power acknowledgment, confirming the power-on request initiated by the ONOFF pin. If neither the PACK bit (D4) in the PON register or the POWERACK pin is set within 128 ms (maximum) of the start of the power-up sequencer, the LP3910 is automatically turned off, as the system has failed to acknowledge the power-on request. Connecting the battery is considered a power-on event. However, hot insertion of the battery with the adapter connected is NOT permitted.

8.4.2.5 Transitioning From Active Mode to Standby Mode

8.4.2.5.1 External Event Triggers the Transition From Active to Standby Mode

When the device is active, a subsequent re-assertion of the push button turns off the LP3910 indirectly by first flagging the system processor though the ONSTAT pin. Upon detecting the ONSTAT transition, the system processor must clear bit D4 (PACK) in the power on event register and apply a logic low to the POWERACK pin to power down the LP3910, which then transitions to Standby Mode. Clearing the PACK register bit and POWERACK pin while external supply sources are present (either USB or CHG_IN) does not power down the LP3910, to keep the charger active. The system can as always disable all necessary DC-DC converters, except Buck1, through the register control.

When external power is disconnected, LP3910 remains in its active state unless the battery voltage is below V_BLA (battery low alarm) or unless the PACK (either bit D4 in the PON register and the POWERACK pin) is cleared by the system processor.

Figure 67. Power-Down Event Caused by External Event

8.4.2.5.2 Transition From Active to Standby Mode Due to Expiring POWERACK Deadline

With no external charger present when the system processor fails to acknowledge the power-on in time by setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128-ms deadline following the start of the power-up sequencer, then the NRST is immediately de-asserted and after 2 ms all power sources are disabled before transitioning to Standby Mode. This 2-ms delay allows the microprocessor to receive a clean reset before the power is de-asserted. A new power-on event is then required to transition back to active mode.

With either external charger present when the system processor fails to acknowledge the power-on in time by setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128-ms deadline following the start of the power-up sequencer, the NRST is immediately de-asserted; after 2 ms all power sources are disabled before transitioning to charger standby mode.

Figure 68. Power Down Caused by Expiring PowerACK Deadline

8.5.1.1 I²C Signals

The LP3910 features an I²C-compatible serial interface, using two dedicated pins: I²C_SCL and I²C_SDA for I²C clock and data, respectively. Both signals need a pullup resistor according to the I²C specification. The LP3910 interface is an I²C slave that is clocked by the incoming SCL clock.

Signal timing specifications are according to the I²C bus specification. The maximum bit rate is 400 kbit/s. See I²C specification from NXP for further details.

8.5.1.2 I²C Data Validity

The data on I²C_SDA line must be stable during the HIGH period of the clock signal (I²C_SCL); that is, the state of the data line can only be changed when CLK is LOW.

Figure 69. I²C Data Valid Diagram

8.5.1.3 I²C Start and Stop Conditions

START and STOP bits classify the beginning and the end of the I²C session. The START condition is defined the as the I²C_SDA signal transitioning from HIGH to LOW while SCL line is HIGH. The STOP condition is defined as the SDA transitioning from LOW to HIGH while I²C_SCL is HIGH. The I²C master always generates START and STOP bits. The I²C bus is considered to be busy after a START condition and free after a STOP condition. During data transmission, I²C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.

Figure 70. Start and Stop Conditions

8.5.1.4 Transferring Data

Every byte put on the I²C_SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated by the master. The transmitter releases the I²C_SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the I²C_SDA line during the 9th clock pulse, signifying acknowledgement. A receiver which has been addressed must generate an acknowledgement (ACK) after each byte has been received.

8.5.1.5 Register Write Cycle

After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). For the eighth bit, a 0 indicates a WRITE, and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data that is written to the selected register.

LP3910 has a chip address of 60’h, which is set by a metal mask option.

Figure 71. I²C Chip Address

w = write (I²C_SDA = 0)
r = read (I²C_SDA = 1)
ack = acknowledge (I²C_SDA pulled down by either master or slave)
rs = repeated start
id = LP3910 chip address: 60’h

Figure 72. I²C Write Cycle

8.5.1.6 Register Read Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown Figure 73.

Figure 73. I²C Read Cycle

8.5.1.7 Multi-Byte I²C Command Sequence

The I²C serial interface of the LP3910 device supports random register multi-byte command sequencing: during a multi-byte write the Master sends the Start command followed by the device address, which is sent only once, followed by the 8-bit register address, then 8 bits of data, The I²C slave must then accept the next random register address followed by 8 bits of data and continue this process until the master sends a valid stop condition.

A typical multi-byte random register transfer is: Device Address,  Register A Address, Ack, Register A Data, Ack Register M Address, Ack, Register M Data, Ack Register X Address, Ack, Register X Data, Ack Register Z Address, Ack, Register Z Data, Ack, Stop

Figure 74. Example Multi-Byte Command Sequencing

Table 11. LDO2 Control Register (09)H

Table 12. Buck1 Control Register (05)H

Table 13. Buck2 Control Register (06)H

Table 14. Buck–Boost Control Register (07)H