SNVS481 Data sheet

SNVS481M November 2006 – December 2015 LP3910

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

NJV|48
- MPQS024

Thermal pad, mechanical data (Package|Pins)

Orderable Information

11 Layout

11.1 Layout Guidelines

For good performance of the circuit, it is essential to place the input and output capacitors very close to the circuit, using wide routing for the traces to allow high currents. Sensitive components must be placed far from those components with high pulsating current, and decoupling capacitors must be placed close to circuit VIN pins. Digital and analog grounds must be routed separately and connected together in a star connection. It is good practice to minimize high current and switching current paths.

11.1.1 LDO Regulators

Place the filter capacitors very close to the input and output pins. Use large trace width for high current-carrying traces and the returns to ground.

11.1.2 Buck and Buck-Boost Regulators

Place the supply bypass, filter capacitor, and inductor close together, keeping the traces short. The traces between these components carry relatively high switching current and act as antennas. Following these rules reduces radiated noise. Arrange the components so that the switching current loops curl in the same direction.

Connect the buck ground and the ground of the capacitors together using generous component-side copper fill as a pseudo-ground plane. Connect the grounds to the general board system ground plane at a single point. Place the pseudo-ground plane below these components and then have it tied to system ground of the output capacitor outside of the current loops. This prevents the switched current from injecting noise into the system ground. These components, along with the inductor and output, must be placed on the same side of the circuit board, and their connections must be made on the same layer.

Route the noise sensitive traces such as the voltage feedback path away from the inductor. This is done by routing it on the bottom layer or by adding a grounded copper area between switching node and feedback path. Noisy traces between the power components and keep any digital lines away from this section. Keep the feedback node as small as possible so that the ground pin and ground traces shield the feedback node from the SW or buck output.

Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses.

11.2 Layout Example

Figure 84. LP3910 Layout Example

11.3 Thermal Performance of the WQFN Package

The LP3910 is a monolithic device with integrated power FETs. For that reason, it is important to pay special attention to the thermal impedance of the WQFN package and to the PCB layout rules in order to maximize power dissipation of the WQFN package.

The WQFN package is designed for enhanced thermal performance and features an exposed die attach pad at the bottom center of the package that creates a direct path to the PCB for maximum power dissipation. Compared to the traditional leaded packages where the die attach pad is embedded inside the molding compound, the WQFN reduces one layer in the thermal path.

The thermal advantage of the WQFN package is fully realized only when the exposed die-attach pad is soldered down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. Based on thermal analysis of the WQFN package, the junction-to-ambient thermal resistance (R_θJA) can be improved by a factor of two when the die attach pad of the WQFN package is soldered directly onto the PCB with thermal land and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. Typical pitch and outer diameter for thermal vias are 1.27 mm and 0.33 mm, respectively. Typical copper via barrel plating is 1 oz., although thicker copper may be used to further improve thermal performance. The LP3910 die attach pad is connected to the substrate of the device and therefore, the thermal land and vias on the PCB board need to be connected to ground (GND pin).

For more information on board layout techniques, refer to AN-1187 Leadless Leadframe Package (LLP) (SNOA401). This application note also discusses package handling, solder stencil, and the assembly process.