The LP3982 low-dropout (LDO) CMOS linear regulator is available in 1.8-V, 2.5-V, 2.82-V, 3-V,
3.3-V, and adjustable versions. They deliver 300 mA of output current. Packaged in an 8-pin VSSOP, the LP3982 is pin- and package-compatible with Maxim's MAX8860. The LM3982 is also available in the small footprint WSON package.
The LP3982 suits battery-powered applications because of its shutdown mode (1 nA typical), low quiescent current (90 μA typical), and LDO voltage (120 mV typical). The low dropout voltage allows for more utilization of a battery’s available energy by operating closer to its end-of-life voltage. The LP3982 device's PMOS output transistor consumes relatively no drive current compared to PNP LDO regulators.
This PMOS regulator is stable with small ceramic capacitive loads (2.2 μF typical).
These devices also include regulation fault detection, a bandgap voltage reference, constant current limiting, and thermal-overload protection.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LP3982 | WSON (8) | 2.50 mm × 3.00 mm |
VSSOP (8) | 3.00 mm × 3.00 mm |
Changes from E Revision (October 2015) to F Revision
Changes from D Revision (April 2013) to E Revision
Changes from C Revision (April 2013) to D Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CC | 6 | — | Connect a capacitor between CC pin and ground to reduce the output noise. The optimum value for CC is 33 nF. |
FAULT | 8 | Output | FAULT pin goes low during out of regulation conditions like current limit and thermal shutdown, or when it approaches dropout. Requires a pullup resistor because it is an active-low, open-drain output. |
GND | 3 | Ground | Ground |
IN | 2 | Input | This is the input supply voltage to the regulator. |
OUT | 1, 4 | Output | Regulated output voltage |
SET | 5 | Input | In the adjustable version a resistor divider connected to this pin sets the output voltage. The SET pin is internally disconnected for the fixed versions. |
SHDN | 7 | Input | The SHDN pin allows the part to be turned to an ON or OFF state by pulling SHDN pin high or low. |
DAP | √ | — | WSON Only - The DAP (Die Attached Pad) is an exposed pad that does not have an internal connection; it functions as a thermal relief when soldered to a copper plane. It is recommend that the DAP be connected to GND. See WSON Mounting section for more information. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN, VOUT, VSHDN, VSET, VCC, VFAULT | −0.3 | 6.5 | V | |
Fault sink current | 20 | mA | ||
Power dissipation | See(4) | |||
Junction temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –65 | 160 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Machine model | ±200 | V |
MIN | NOM | MAX | UNIT | |
---|---|---|---|---|
Operating temperature | –40 | 85 | °C | |
Supply voltage | 2.5 | 6 | V |
THERMAL METRIC(1) | LP3982 | UNIT | ||
---|---|---|---|---|
DGK (VSSOP) | NGM (WSON)(2) | |||
8 PINS | 8 PINS | |||
RθJA(3) | Junction-to-ambient thermal resistance, High-K | 175.2 | 52.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 66.0 | 66.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 95.6 | 16.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 9.7 | 1.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 94.2 | 16.7 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | 11.1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN(2) | TYP(3) | MAX(2) | UNIT | |
---|---|---|---|---|---|---|
VIN | Input voltage | For operating temperature extremes: −40°C to 85°C | 2.5 | 6 | V | |
ΔVOUT | Output voltage tolerance | 100 μA ≤ IOUT ≤ 300 mA VIN = VOUT + 0.5 V(1) SET = OUT for the ADJ Versions |
−2 | 2 | % of VOUT (NOM) | |
For operating temperature extremes: −40°C to 85°C | −3 | 3 | ||||
VOUT | Output adjust range | ADJ version only; for operating temperature extremes: −40°C to 85°C |
1.25 | 6 | V | |
IOUT | Maximum output current | Average DC current rating; For operating temperature extremes: −40°C and 85°C |
300 | mA | ||
ILIMIT | Output current limit | 770 | mA | |||
For operating temperature extremes: −40°C to 85°C | 330 | |||||
IQ | Supply current | IOUT = 0 mA | 90 | μA | ||
IOUT = 0 mA; for operating temperature extremes: −40°C to 85°C |
270 | |||||
IOUT = 300 mA | 225 | |||||
Shutdown supply current | VO = 0 V, SHDN = GND | 0.001 | 1 | μA | ||
VDO | Dropout voltage(1)(4) | IOUT = 1 mA | 0.4 | mV | ||
IOUT = 200 mA | 80 | |||||
IOUT = 200 mA; for operating temperature extremes: −40°C to 85°C |
220 | |||||
IOUT = 300 mA | 120 | |||||
ΔVOUT | Line regulation | IOUT = 1 mA, (VOUT + 0.5 V) ≤ VI ≤ 6 V(1) |
0.01 | %/V | ||
IOUT = 1 mA, (VOUT + 0.5 V) ≤ VI ≤ 6 V(1); for operating temperature extremes: −40°C to 85°C |
−0.1 | 0.1 | ||||
Load regulation | 100 μA ≤ IOUT ≤ 300 mA | 0.002 | %/mA | |||
en | Output voltage noise | IOUT = 10 mA, 10 Hz ≤ f ≤ 100 kHz | 37 | μVRMS | ||
Output voltage noise density | 10 Hz ≤ f ≤ 100 kHz, COUT = 10 μF | 190 | nV/√Hz | |||
VSHDN | SHDN input threshold | VIH, (VOUT + 0.5 V) ≤ VIN ≤ 6 V(1); for operating temperature extremes: −40°C to 85°C |
2 | V | ||
VIL, (VOUT + 0.5 V) ≤ VIN ≤ 6 V(1); for operating temperature extremes:−40°C to 85°C |
0.4 | |||||
ISHDN | SHDN input bias current | SHDN = GND or IN | 0.1 | 100 | nA | |
ISET | SET input leakage | SET = 1.3 V, ADJ version only(5) | 0.1 | 2.5 | nA | |
VFAULT | FAULT detection voltage | VO ≥ 2.5 V, IOUT = 200 mA(6) | 120 | mV | ||
VOUT ≥ 2.5 V, IOUT = 200 mA(6); for operating temperature extremes: −40°C to 85°C |
280 | |||||
FAULT output low voltage | ISINK = 2 mA | 0.115 | V | |||
ISINK = 2 mA; for operating temperature extremes: −40°C to 85°C |
0.25 | |||||
IFAULT | FAULT off-leakage current | FAULT = 3.6 V, SHDN = 0 V | 0.1 | 100 | nA | |
TSD | Thermal shutdown temperature | 160 | °C | |||
Thermal shutdown hysteresis | 10 | |||||
TON | Start-up time | COUT = 10 μF, VOUT at 90% of final value | 120 | μs |