LP3982 Micropower, Ultra-Low-Dropout, Low-Noise, 300-mA CMOS Regulator
- SNVS185F February 2002 – April 2017 LP3982
  
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DATA SHEET

LP3982 Micropower, Ultra-Low-Dropout, Low-Noise, 300-mA CMOS Regulator

1 Features

2.5-V to 6-V Input Range
MAX8860 Pin, Package, and Specification Compatible
300-mA Output Current
120-mV Typical Dropout at 300 mA
90-μA Typical Quiescent Current
1-nA Typical Shutdown Mode
60-dB Typical PSRR
120-μs Typical Turnon Time
Stable With Small Ceramic Output Capacitors
37-μV_RMS Output Voltage Noise
(10 Hz to 100 kHz)
Overtemperature/Overcurrent Protection
±2% Output Voltage Tolerance
Create a Custom Design Using the LP3982 With the WEBENCH® Power Designer

2 Applications

Wireless Handsets
DSP Core Power
Battery Powered Electronics
Portable Information Appliances

3 Description

The LP3982 low-dropout (LDO) CMOS linear regulator is available in 1.8-V, 2.5-V, 2.82-V, 3-V,
3.3-V, and adjustable versions. They deliver 300 mA of output current. Packaged in an 8-pin VSSOP, the LP3982 is pin- and package-compatible with Maxim's MAX8860. The LM3982 is also available in the small footprint WSON package.

The LP3982 suits battery-powered applications because of its shutdown mode (1 nA typical), low quiescent current (90 μA typical), and LDO voltage (120 mV typical). The low dropout voltage allows for more utilization of a battery’s available energy by operating closer to its end-of-life voltage. The LP3982 device's PMOS output transistor consumes relatively no drive current compared to PNP LDO regulators.

This PMOS regulator is stable with small ceramic capacitive loads (2.2 μF typical).

These devices also include regulation fault detection, a bandgap voltage reference, constant current limiting, and thermal-overload protection.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LP3982	WSON (8)	2.50 mm × 3.00 mm
LP3982	VSSOP (8)	3.00 mm × 3.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Application Circuit (Fixed V_OUT Version)

4 Revision History

Changes from E Revision (October 2015) to F Revision

Added links for Webench and changed top navigator icon for TI Designs Go

Changes from D Revision (April 2013) to E Revision

Added Device Information and Pin Configuration and Functions sections, ESD Ratings table, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; update Thermal InformationGo
Deleted lead temperature from Abs Max table (in POA); revised wording for footnote 4 Go

Changes from C Revision (April 2013) to D Revision

Changed layout of National Data Sheet to TI formatGo

5 Pin Configuration and Functions

DGK Package

8-Pin VSSOP

Top View

The SET pin is internally disconnected for the fixed versions.

NGM Package

8-Pin WSON With Thermal Pad

Top View

The SET pin is internally disconnected for the fixed versions.

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
CC	6	—	Connect a capacitor between CC pin and ground to reduce the output noise. The optimum value for CC is 33 nF.
FAULT	8	Output	FAULT pin goes low during out of regulation conditions like current limit and thermal shutdown, or when it approaches dropout. Requires a pullup resistor because it is an active-low, open-drain output.
GND	3	Ground	Ground
IN	2	Input	This is the input supply voltage to the regulator.
OUT	1, 4	Output	Regulated output voltage
SET	5	Input	In the adjustable version a resistor divider connected to this pin sets the output voltage. The SET pin is internally disconnected for the fixed versions.
SHDN	7	Input	The SHDN pin allows the part to be turned to an ON or OFF state by pulling SHDN pin high or low.
DAP	√	—	WSON Only - The DAP (Die Attached Pad) is an exposed pad that does not have an internal connection; it functions as a thermal relief when soldered to a copper plane. It is recommend that the DAP be connected to GND. See WSON Mounting section for more information.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

	MIN	MAX	UNIT
V_IN, V_OUT, V_SHDN, V_SET, V_CC, V_FAULT	−0.3	6.5	V
Fault sink current		20	mA
Power dissipation	See⁽⁴⁾
Junction temperature, T_J		150	°C
Storage temperature, T_stg	–65	160	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pin.

(3) If Military/Aerospace-specified devices are required, contact Texas Instruments Sales Office/Distributors for availability and specifications.

(4) In applications where high power dissipation and/or poor thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T_A(MAX)) is dependant on the maximum operating junction temperature (T_J(MAX-OP)), the maximum power dissipation (P_D(MAX)), and the junction-to-ambient thermal resistance in the application (R_θJA). This relationship is given by: T_A(MAX) = T_J(MAX-OP) − (P_D(MAX) × R_θJA).The value of the R_θJA for the WSON package is specifically dependent on the PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the WSON package, refer to TI Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Machine model	±200	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions⁽¹⁾⁽²⁾

	MIN	NOM	MAX	UNIT
Operating temperature	–40		85	°C
Supply voltage	2.5		6	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LP3982		UNIT
		DGK (VSSOP)	NGM (WSON)⁽²⁾
		8 PINS	8 PINS
R_θJA⁽³⁾	Junction-to-ambient thermal resistance, High-K	175.2	52.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	66.0	66.2	°C/W
R_θJB	Junction-to-board thermal resistance	95.6	16.7	°C/W
ψ_JT	Junction-to-top characterization parameter	9.7	1.9	°C/W
ψ_JB	Junction-to-board characterization parameter	94.2	16.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	11.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) The PCB for the WSON/NGN package R_θJA includes thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.

(3) Thermal resistance value R_θJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

6.5 Electrical Characteristics

Unless otherwise specified, all limits are specified for V_IN = V_OUT + 0.5 V⁽¹⁾, V_SHDN = V_IN, C_IN = C_OUT = 2.2 μF, C_CC = 33 nF, T_J = 25°C.

PARAMETER		TEST CONDITIONS	MIN⁽²⁾	TYP⁽³⁾	MAX⁽²⁾	UNIT
V_IN	Input voltage	For operating temperature extremes: −40°C to 85°C	2.5		6	V
ΔV_OUT	Output voltage tolerance	100 μA ≤ I_OUT ≤ 300 mA V_IN = V_OUT + 0.5 V⁽¹⁾ SET = OUT for the ADJ Versions	−2		2	% of V_{OUT (NOM)}
ΔV_OUT	Output voltage tolerance	For operating temperature extremes: −40°C to 85°C	−3		3	% of V_{OUT (NOM)}
V_OUT	Output adjust range	ADJ version only; for operating temperature extremes: −40°C to 85°C	1.25		6	V
I_OUT	Maximum output current	Average DC current rating; For operating temperature extremes: −40°C and 85°C	300			mA
I_LIMIT	Output current limit			770		mA
I_LIMIT	Output current limit	For operating temperature extremes: −40°C to 85°C	330			mA
I_Q	Supply current	I_OUT = 0 mA		90		μA
		I_OUT = 0 mA; for operating temperature extremes: −40°C to 85°C			270
		I_OUT = 300 mA		225
	Shutdown supply current	V_O = 0 V, SHDN = GND		0.001	1	μA
V_DO	Dropout voltage⁽¹⁾⁽⁴⁾	I_OUT = 1 mA		0.4		mV
		I_OUT = 200 mA		80
		I_OUT = 200 mA; for operating temperature extremes: −40°C to 85°C			220
		I_OUT = 300 mA		120
ΔV_OUT	Line regulation	I_OUT = 1 mA, (V_OUT + 0.5 V) ≤ V_I ≤ 6 V⁽¹⁾		0.01		%/V
	Line regulation	I_OUT = 1 mA, (V_OUT + 0.5 V) ≤ V_I ≤ 6 V⁽¹⁾; for operating temperature extremes: −40°C to 85°C	−0.1		0.1	%/V
	Load regulation	100 μA ≤ I_OUT ≤ 300 mA		0.002		%/mA
e_n	Output voltage noise	I_OUT = 10 mA, 10 Hz ≤ f ≤ 100 kHz		37		μV_RMS
e_n	Output voltage noise density	10 Hz ≤ f ≤ 100 kHz, C_OUT = 10 μF		190		nV/√Hz
V_SHDN	SHDN input threshold	V_IH, (V_OUT + 0.5 V) ≤ V_IN ≤ 6 V⁽¹⁾; for operating temperature extremes: −40°C to 85°C	2			V
V_SHDN	SHDN input threshold	V_IL, (V_OUT + 0.5 V) ≤ V_IN ≤ 6 V⁽¹⁾; for operating temperature extremes:−40°C to 85°C			0.4	V
I_SHDN	SHDN input bias current	SHDN = GND or IN		0.1	100	nA
I_SET	SET input leakage	SET = 1.3 V, ADJ version only⁽⁵⁾		0.1	2.5	nA
V_FAULT	FAULT detection voltage	V_O ≥ 2.5 V, I_OUT = 200 mA⁽⁶⁾		120		mV
	FAULT detection voltage	V_OUT ≥ 2.5 V, I_OUT = 200 mA⁽⁶⁾; for operating temperature extremes: −40°C to 85°C			280	mV
	FAULT output low voltage	I_SINK = 2 mA		0.115		V
	FAULT output low voltage	I_SINK = 2 mA; for operating temperature extremes: −40°C to 85°C			0.25	V
I_FAULT	FAULT off-leakage current	FAULT = 3.6 V, SHDN = 0 V		0.1	100	nA
T_SD	Thermal shutdown temperature			160		°C
T_SD	Thermal shutdown hysteresis			10		°C
T_ON	Start-up time	C_OUT = 10 μF, V_OUT at 90% of final value		120		μs

(1) Condition does not apply to input voltages below 2.5 V because this is the minimum input operating voltage.

(2) All limits are verified by testing or statistical analysis.

(3) Typical values represent the most likely parametric norm.

(4) Dropout voltage is measured by reducing V_IN until V_OUT drops 100 mV from its nominal value at V_IN – V_OUT = 0.5 V. Dropout voltage does not apply to the 1.8-V version.

(5) The SET pin is not externally connected for the fixed versions.

(6) The FAULT detection voltage is specified for the input-to-output voltage differential at which the FAULT pin goes active low.