SLAS928 Data sheet

SLAS928B March 2013 – November 2016 LP3988-Q1

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DBV|5

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
Voltage	−0.3	6.5	V
Power Good (OUT, EN)	−0.3	See⁽³⁾	V
Junction temperature, T_J		150	°C
Power dissipation⁽⁴⁾		469	mW
Storage temperature, T_stg	−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pin.

(3) The lesser of V_IN + 0.3 V or 6 V.

(4) The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: P_D = (T_J – T_A) / R_θJA, where T_J is the junction temperature, T_A is the ambient temperature, and R _θJA is the junction-to-ambient thermal resistance. The 469-mW rating appearing under Absolute Maximum Ratings for the 5-pin SOT-23 package results from substituting the absolute-maximum junction temperature, 150°C, for T_J, 70°C for T_A, and 170.5°C/W for R_θJA. More power can be dissipated safely at ambient temperatures below 70°C . Less power can be dissipated safely at ambient temperatures above 70°C. The absolute-maximum power dissipation can be increased by 5.86 mW for each degree below 70°C, and it must be derated by 5.86 mW for each degree above 70°C.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±750	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
IN⁽²⁾	2.5	6	V
OUT, EN	0	V_IN	V
Junction temperature, T_J	–40	125	°C

(1) All voltages are with respect to the potential at the GND pin.

(2) The minimum V_IN is dependant on the device output option. For V_OUT(NOM) < 2.5 V, V_IN(MIN) equals 2.5 V. For V_OUT(NOM) ≥ 2.5 V, V_IN(MIN) equals V_OUT(NOM) + 200 mV.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LP3988-Q1	UNIT
		DBV (SOT-23)
		5 PINS
R_θJA⁽²⁾	Junction-to-ambient thermal resistance, High-K	170.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	124.4	°C/W
R_θJB	Junction-to-board thermal resistance	30.9	°C/W
ψ_JT	Junction-to-top characterization parameter	17.6	°C/W
ψ_JB	Junction-to-board characterization parameter	30.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics.

(2) Thermal resistance value R_θJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

6.5 Electrical Characteristics

Unless otherwise specified: V_EN = 1.8 V, V_IN = V_OUT + 0.5 V, C_IN = 1 µF, I_OUT = 1 mA, C_OUT = 1 µF; typical values and limits are for T_J = 25°C, and minimum and maximum values and limits apply over the entire junction temperature range for operation, −40°C to +125°C.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ΔV_OUT	Output voltage tolerance	T_J = 25°C	−2		2	% of V_OUT(NOM)
	Output voltage tolerance		–3.5		3.5	% of V_OUT(NOM)
	Line regulation error	V_IN = V_OUT(NOM) + 0.5 V to 6 V T_J = 25°C	−0.15		0.15	%/V
	Line regulation error	V_IN = V_OUT(NOM) + 0.5 V to 6 V	–0.2		0.2	%/V
	Load regulation error⁽³⁾	I_OUT = 1 mA to 150 mA, T_J = 25°C			0.005	%/mA
	Load regulation error⁽³⁾	I_OUT = 1 mA to 150 mA			0.007	%/mA
PSRR	Power supply rejection ratio	V_IN = V_OUT(NOM) + 1 V, ƒ = 1 kHz, I_OUT = 50 mA (See Figure 15)		65		dB
PSRR	Power supply rejection ratio	V_IN = V_OUT(nom) + 1 V, ƒ = 10 kHz, I_OUT = 50 mA (See Figure 15)		45		dB
I_Q	Quiescent current	V_EN = 1.4 V, I_OUT = 0 mA, T_J = 25°C		85	120	µA
		V_EN = 1.4 V, I_OUT = 0 to 150 mA		140	200
		V_EN = 0.4 V		0.003	1
V_DO	Dropout voltage⁽⁴⁾	I_OUT = 1 mA		1	5	mV
		I_OUT = 150 mA, T_J = 25°C		80	115	mV
		I_OUT = 150 mA			150
I_SC	Short-circuit current limit	See⁽⁵⁾		600		mA
e_n	Output noise voltage	BW = 10 Hz to 100 kHz, C_OUT = 1 µF		220		µV_RMS
C_OUT	Output capacitor	Capacitance⁽⁶⁾	1		20	µF
C_OUT	Output capacitor	ESR⁽⁶⁾	5		500	mΩ
TSD	Thermal shutdown temperature			160		°C
TSD	Thermal shutdown hysteresis			20		°C
ENABLE CONTROL CHARACTERISTICS
I_EN	Maximum input current at EN	V_EN = 0 V and V_IN = 6 V			0.1	µA
V_IL	Logic low input threshold	V_IN = 2.5 V to 6 V			0.5	V
V_IH	Logic high input threshold	V_IN = 2.5 V to 6 V	1.2			V
POWER GOOD
V_THL	PG low threshold	% of V_OUT (PG ON), T_J = 25°C⁽⁷⁾	90%	93%	95%
V_THH	PG high threshold	% of V_OUT (PG OFF), T_J = 25°C⁽⁷⁾	92%	95%	98%
V_OL	PG output logic low voltage	I_PULLUP = 100 µA, fault condition		0.02	0.1	V
I_PGL	PG output leakage current	PG off, V_PG = 6 V		0.02		µA

(1) All electrical characteristics having room-temperature limits are tested during production with T_J = 25°C or correlated using statistical quality control (SQC) methods. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(2) The target output voltage, which is labeled V_OUT(NOM), is the desired voltage option.

(3) An increase in the load current results in a slight decrease in the output voltage and vice versa.

(4) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.

(5) Short-circuit current is measured on input supply line after pulling down V_OUT to 95% V_OUT(NOM).

(6) Specified by design. Not production tested. The capacitor tolerance should be ±30% or better over the full temperature range. The full range of operating conditions such as temperature, DC bias and even capacitor case size for the capacitor in the application must be considered during device selection to ensure this minimum capacitance specification is met. TI recommends X7R capacitor types to meet the full device temperature range.

(7) The low and high thresholds are generated together. Typically a 2.6% difference is seen between these thresholds.