The LP3990 regulator is designed to meet the requirements of portable, battery-powered systems providing an accurate output voltage, low-noise, and low-quiescent current. The LP3990 will provide a 0.8-V output from the low input voltage of 2 V at up to a 150-mA load current. When switched into shutdown mode via a logic signal at the enable pin (EN), the power consumption is reduced to virtually zero.
The LP3990 is designed to be stable with space-saving ceramic capacitors with values as low as 1 µF.
Performance is specified for a –40°C to 125°C junction temperature range.
For output voltages other than 0.8 V, 1.2 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V, 2.8 V, or 3.3 V, please contact the Texas Instruments sales office.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LP3990 | DSBGA (4) | 1.324 mm x 1.045 mm (MAX) |
WSON (6) | 2.90 mm x 1.60 mm | |
SOT-23 (5) | 3.00 mm x 3.00 mm |
Changes from I Revision (May 2013) to J Revision
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | DSBGA | SOT-23 | WSON | ||
YZR | DBV | NGG | |||
GND | A1 | 2 | 2 | — | Common Ground. |
EN | A2 | 3 | 5 | I | Enable Input; Enables the Regulator when ≥ 0.95 V. Disables the Regulator when ≤ 0.4 V. Enable Input has 1-MΩ (typical) pull-down resistor to GND. |
OUT | B1 | 5 | 1 | O | Voltage output. A 1-µF Low ESR Capacitor should be connected to this Pin. Connect this output to the load circuit. |
IN | B2 | 1 | 6 | I | Voltage supply Input. A 1-µF capacitor should be connected at this input. |
N/A | 4 | 3 | I | No internal connection. | |
N/C | N/A | 4 | I | No internal connection. | |
N/C | Pad | — | Thermal pad. Connect to Pin 2. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | –0.3 | 6.5 | V | |
Output voltage | –0.3 | Note(4) | ||
ENABLE input voltage | –0.3 | 6.5 | ||
Continuous power dissipation internally limited | Note(5) |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature range | –65 | 150 | °C | |
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | –2000 | 2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins | 250 | 1500 | |||
Machine model | –200 | 200 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Input voltage, VIN | 2 | 6 | V | ||
Enable input voltage, VEN | 0.0 | VIN | |||
Junction temperature, TJ(1) | –40 | 125 | °C |
THERMAL METRIC(1) | LP3990 | UNIT | |||
---|---|---|---|---|---|
YZR (DSBGA) | DBV (SOT-23) | NGG (WSON) | |||
4 PINS | 5 PINS | 6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 188.9 | 165.2 | 53.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 1.0 | 69.9 | 51.2 | |
RθJB | Junction-to-board thermal resistance | 105.3 | 27.3 | 28.2 | |
ψJT | Junction-to-top characterization parameter | 0.7 | 1.8 | 0.6 | |
ψJB | Junction-to-board characterization parameter | 105.2 | 26.8 | 28.3 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | 8.1 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIN | Input voltage | Note (2), TJ = 25°C | 2 | 6 | V | ||
ΔVOUT | Output voltage tolerance | ILOAD = 1 mA TJ = 25°C |
DSBGA | –1 | 1% | ||
WQFN | –1.5% | 1.5% | |||||
SOT-23 | –1.5% | 1.5% | |||||
Over full line and load regulation | DSBGA | –2.5% | 2.5% | ||||
WQFN | –3% | 3% | |||||
SOT-23 | –4% | 4% | |||||
Line regulation error | VIN = (VOUT(NOM) + 1 V) to 6 V | 0.1 | 0.02 | 0.1 | %/V | ||
Load regulation error | IOUT = 1 mA to 150 mA |
VOUT = 0.8 V to 1.95 V DSBGA |
–0.005 | 0.002 | 0.005 | %/mA | |
VOUT = 0.8 V to 1.95 V WQFN, SOT-23 |
–0.008 | 0.003 | 0.008 | ||||
VOUT = 2 V to 3.3 V DSBGA |
–0.002 | 0.0005 | 0.002 | ||||
VOUT = 2 V to 3.3 V WQFN, SOT-23 |
–0.005 | 0.002 | 0.005 | ||||
VDO | Dropout voltage | IOUT = 150 mA(4)(5) | 120 | 200 | mV | ||
ILOAD | Load current | Note (5)(6), TJ = 25°C | 0 | µA | |||
IQ | Quiescent current | VEN = 950 mV, IOUT = 0 mA | 43 | 80 | µA | ||
VEN = 950 mV, IOUT = 150 mA | 65 | 120 | |||||
VEN = 0.4 V (output disabled), TJ = 25°C | 0.002 | 0.2 | |||||
ISC | Short circuit current limit | Note (7) | 550 | 1000 | mA | ||
IOUT | Maximum output current | 150 | |||||
PSRR | Power Supply Rejection Ratio | ƒ = 1 kHz, IOUT = 1 mA to 150 mA | 55 | dB | |||
ƒ = 10 kHz, IOUT = 150 mA | 35 | ||||||
eη | Output noise voltage(5) | BW = 10 Hz to 100 kHz | VOUT = 0.8 V | 60 | µVRMS | ||
VOUT = 1.5 V | 125 | ||||||
VOUT = 3.3 V | 180 | ||||||
TSHUTDOWN | Thermal shutdown junction temperature | Junction temperature (TJ) rising until the output is disabled | 155 | °C | |||
Hysteresis | 15 | ||||||
ENABLE CONTROL CHARACTERISTICS | |||||||
IEN(8) | Maximum input current at EN pin | VEN = 0 V (Output is disabled) TJ = 25°C |
0.001 | 0.1 | µA | ||
VEN = 6 V | 2.5 | 6 | 10 | ||||
VIL | Low input threshold | VIN = 2 V to 6 V VEN falling from ≥ VIH until the output is disabled |
0.4 | V | |||
VIH | High input threshold | VIN = 2 V to 6 V VEN rising from ≤ VIL until the output is enabled |
0.95 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
COUT | Output capacitance | Capacitance(3) | 0.7(2) | 1 | 500 | µF |
ESR | 5 | mΩ |
MIN | NOM(1) | MAX(2) | UNIT | ||||
---|---|---|---|---|---|---|---|
TON | Turnon time (3) | From VEN ↑ VIH to VOUT 95% level (VIN(MIN) to 6 V) |
VOUT = 0.8 V | 80 | 150 | µs | |
VOUT = 1.5 V | 105 | 200 | |||||
VOUT = 3.3 V | 175 | 250 | |||||
Transient response | Line transient response (ΔVOUT) | Trise = Tfall = 30 µs(3), ΔVIN = 600 mV |
8 | 16 | mV (pk-pk) | ||
Load transient response (ΔVOUT) | Trise = Tfall = 1 µs(3), IOUT = 1 mA to 150 mA COUT = 1 µF |
55 | 100 | mV |
ILOAD = 0 mA | ||
ILOAD = 150 mA | ||
ILOAD = 1 mA | ||
Designed meet the requirements of portable, battery-powered digital systems providing an accurate output voltage with fast start-up. When disabled via a low logic signal at the enable pin (EN), the power consumption is reduced to virtually zero
The LP3990 is designed to perform with a single 1-μF input capacitor and a single 1-μF ceramic output capacitor.
The LP3990 Enable (EN) pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the VIL threshold to ensure that the device is fully disabled. If the EN pin is left open the LP3990 output will be disabled.
Thermal Shutdown disables the output when the junction temperature rises to approximately 155°C which allows the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.
The Thermal Shutdown circuitry of the LP3990 has been designed to protect against temporary thermal overload conditions. The Thermal Shutdown circuitry was not intended to replace proper heat-sinking. Continuously running the LP3990 device into thermal shutdown may degrade device reliability.
The LP3990 EN pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions.
The LP3990 does not include any dedicated UVLO circuitry. The LP3990 internal circuitry is not fully functional until VIN is at least 2 V. The output voltage is not regulated until VIN ≥ (VOUT + VDO), or 2 V, whichever is higher.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LP3990 is a linear voltage regulator for digital applications designed to be stable with space-saving ceramic capacitors as small as 1 µF.
Figure 13 shows the typical application circuit for the LP3990. The input and output capacitances may need to be increased above the 1 μF shown for some applications.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage range | 2 V to 6 V |
Output voltage | 1.8 V |
Output current | 100 mA |
Output capacitor range | 1 µF |
Input/output capacitor ESR range | 5 mΩ to 500 mΩ |
To begin the design process, determine the following:
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die junction and ambient air.
The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1:
The actual power being dissipated in the device can be represented by Equation 2:
These two equations establish the relationship between the maximum power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. These two equations should be used to determine the optimum operating conditions for the device in the application.
In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present, the maximum ambient temperature (TA-MAX) may be increased.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature (TA-MAX) may have to be derated. TA-MAX is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by Equation 3:
Alternately, if TA-MAX can not be derated, the PD value must be reduced. This can be accomplished by reducing VIN in the 'VIN–VOUT' term as long as the minimum VIN is met, or by reducing the IOUT term, or by some combination of the two.
In common with most regulators, the LP3990 requires external capacitors for regulator stability. The LP3990 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance.
An input capacitor is required for stability. It is recommended that a 1-µF capacitor be connected between the LP3990 IN pin and GND pin (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: To ensure stable operation it is essential that good PCB design practices are employed to minimize ground impedance and keep input inductance low. If these conditions cannot be met, or if long leads are used to connect the battery or other power source to the LP3990, then it is recommended that the input capacitor is increased. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain approximately 1 µF over the entire operating temperature range.
The LP3990 is designed specifically to work with very small ceramic output capacitors. A 1-µF ceramic capacitor (temperature types Z5U, Y5V or X7R/X5R) with ESR between 5 mΩ to 500 mΩ, is suitable in the LP3990 application circuit.
For this device the output capacitor should be connected between the OUT pin and GND pin.
It is also possible to use tantalum or film capacitors at the device output, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5 mΩ to 500 mΩ for stability.
The LP3990 will remain stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications.
The LP3990 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LP3990.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type.
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer performance figures in general. As an example, Figure 14 shows a typical graph comparing different capacitor case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result in the capacitance value falling below the minimum value given in the recommended capacitor specifications table (0.7 µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (for example, 0402) may not be suitable in the actual application.
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of –55°C to 125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of –55°C to 85°C. Many large value ceramic capacitors, larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R and X5R types are recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47-µF to 4.7-µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to -40°C, so some guard band must be allowed.
The LP3990 features an active high Enable pin, EN, which turns the device on when pulled high. When not enabled the regulator output is off and the device typically consumes 2 nA.
If the application does not require the Enable switching feature, the EN pin should be tied to VIN to keep the regulator output permanently on.
To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH.
An internal 1-MΩ pull-down resistor ties the EN input to ground, ensuring that the device remains off if the EN pin is left open circuit.