SLVSEH1B September 2018 – January 2019 LP5030 , LP5036
PRODUCTION DATA.
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
ƒOSC | Internal oscillator frequency(1) | 15 | MHz | ||
tPSM | Power save mode deglitch time(1) | 20 | 30 | 40 | ms |
tEN_H | EN first rising edge until first I2C access(1) | 500 | µs | ||
tEN_L | EN first falling edge until first I2C reset(1) | 3 | µs | ||
ƒSCL | I2C clock frequency(1) | 400 | kHz | ||
1 | Hold time (repeated) START condition(1) | 0.6 | µs | ||
2 | Clock low time(1) | 1.3 | µs | ||
3 | Clock high time(1) | 600 | ns | ||
4 | Setup time for a repeated START condition(1) | 600 | ns | ||
5 | Data hold time(1) | 0 | ns | ||
6 | Data setup time(1) | 100 | ns | ||
7 | Rise time of SDA and SCL(1) | 20 + 0.1 Cb | ns | ||
8 | Fall time of SDA and SCL(1) | 15 + 0.1 Cb | ns | ||
9 | Setup time for STOP condition(1) | 600 | ns | ||
10 | Bus free time between a STOP and a START condition(1) | 1.3 | µs | ||
Cb | Capacitive load parameter for each bus line Load of 1 pF corresponds to one nanosecond(1). | 10 | 200 | pF |