7.3.1.1 Output Resistance

At lower input voltages, the charge pump output voltage may degrade due to effective output resistance (R_OUT) of the charge pump. The expected voltage drop can be calculated by using a simple model for the charge pump shown in Figure 14.

Figure 14. Charge Pump Block Diagram

The model shows a linear pre-regulation block (REG), a voltage multiplier (1.5×), and an output resistance (R_OUT). Output resistance models the output voltage drop that is inherent to switched capacitor converters. The output resistance is 3.5 Ω (typical) and is function of switching frequency, input voltage, capacitance value of the flying capacitors, internal resistances of switches, and ESR of flying capacitors. When the output voltage is in regulation, the regulator in the model controls the voltage V’ to keep the output voltage equal to 4.5 V (typical). With increased output current, the voltage drop across R_OUT increases. To prevent drop in output voltage, the voltage drop across the regulator is reduced, V’ increases, and V_OUT remains at 4.5 V. When the output current increases to the point that there is zero voltage drop across the regulator, V’ equals the input voltage, and the output voltage is on the edge of regulation. Additional output current causes the output voltage to fall out of regulation, so that the operation is similar to a basic open-loop 1.5× charge pump. In this mode, output current results in output voltage drop proportional to the output resistance of the charge pump. The out-of-regulation output voltage can be approximated by: V_OUT= 1.5 × V_IN – I_OUT × R_OUT.

7.3.1.2 Controlling Charge Pump

The charge pump is controlled with two CP_MODE bits in register 08H. When both bits are low, the charge pump is disabled, and the output voltage is pulled down with 300 kΩ. Charge pump can be forced to bypass mode, so that battery voltage is going directly to RGB outputs. In 1.5× mode output voltage is boosted to 4.5 V. In automatic mode, charge pump operation mode is defined by LED outputs saturation described in LED Forward Voltage Monitoring. Table 1 lists operation modes and selection bits.

7.3.1.3 LED Forward Voltage Monitoring

When charge pump automatic mode selection is enabled, voltages over LED drivers are monitored. If drivers do not have enough headroom, charge pump gain is set to 1.5×. Driver saturation monitor does not have a fixed voltage limit, since saturation voltage is a function of temperature and current. Charge pump gain is set to 1×, when battery voltage is high enough to supply all LEDs.

In automatic gain change mode, charge pump is switched to bypass mode (1×), when LEDs are inactive for over 50 ms.

Charge pump gain control utilizes digital filtering to prevent supply voltage disturbances from triggering gain changes. If the R driver current source is connected to a battery (address 08H, bit R_TO_BATT = 1), voltage monitoring is disabled in R output, but still functional in B and G outputs.

LED forward voltage monitoring and gain control block diagram is shown in Figure 15.

Figure 15. Voltage Monitoring Block Diagram for One Output

Table 2. LED Configuration Examples

Table 3. R_CURRENT Register (05H), G_CURRENT register (06H), B_CURRENT register (07H):

Table 4. ENABLE Register (00H):

Table 5. CONFIG Register (08H):

Table 6. LED Controller Operation

See application note LP5521 Power Efficiency Considerations (SNVA185) for more information.

Table 7. CONFIG Register (08H):

7.3.5.1 I/O Levels

I²C interface, CLK_32K and TRIG pins input levels are defined by EN pin. Using EN pin as voltage reference for logic inputs simplifies PWB routing and eliminates the need for dedicated V_IO pin. Figure 17 describes EN pin connections.

Figure 17. Using EN Pin as Digital I/O Voltage Reference

ADDR_SEL0/1 are referenced to V_DD voltage. GPO pin level is defined by V_DD voltage.

7.3.5.2 GPO/INT Pins

LP5521 has one General Purpose Output pin (GPO); the INT pin can also be configured as a GPO pin. When INT is configured as GPO output, its level is defined by the V_DD voltage. State of the pins can be controlled with GPO register (0EH). GPO pins are digital CMOS outputs and no pullup or pulldown resistors are needed.

When INT pin GPO function is disabled, it operates as an open drain pin. INT signal is active low; that is, when interrupt signal is sent, the pin is pulled to GND. External pullup resistor is needed for proper functionality.

7.3.5.3 TRIG Pin

The TRIG pin can function as an external trigger input or output. External trigger signal is active low; that is, when trigger is sent or received the pin is pulled to GND. TRIG is an open-drain pin and external pullup resistor is needed for trigger line. External trigger input signal must be at least two 32-kHz clock cycles long to be recognized. Trigger output signal is three 32-kHz clock cycles long. If TRIG pin is not used on application, connected the TRIG pin to GND to prevent floating of this pin and extra current consumption.

7.3.5.4 ADDR_SEL0,1 Pins

The ADDR_SEL0,1 pins define the chip I²C address. Pins are referenced to V_DD signal level. See I2C-Compatible Serial Bus Interface for I²C address definitions.

7.3.5.5 CLK_32K Pin

The CLK_32K pin is used for connecting an external 32-kHz clock to LP5521. External clock can be used to synchronize the sequence engines of several LP5521. Using external clock can also improve automatic power save mode efficiency, because internal clock can be switched off automatically when device has entered power save mode, and external clock is present. See application note LP5521 Power Efficiency Considerations (SNVA185) for more information.

Device can be used without the external clock. If external clock is not used on the application, connect the CLK_32K pin to GND to prevent floating of this pin and extra current consumption.

7.5.1.1 Interface Bus Overview

The I²C compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). These lines should be connected to a positive supply, via a pullup resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the serial clock (SCL).

7.5.1.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the high period of the clock the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock.

Figure 19. Data Validity

Each data transaction is composed of a start condition, a number of byte transfers (set by the software) and a stop condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an acknowledge signal must follow. The following sections provide further details of this process.

Figure 20. Acknowledge Signal

The Master device on the bus always generates the start and stop conditions (control codes). After a start condition is generated, the bus is considered busy and it retains this status until a certain time after a stop condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a start condition. A low-to-high transition of the SDA line while the SCL is high indicates a stop condition.

Figure 21. Start and Stop Conditions

In addition to the first start condition, a repeated start condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle.

7.5.1.3 Acknowledge Cycle

The acknowledge cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte.

7.5.1.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

7.5.1.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP5521 operates as a slave device with the 7-bit address. The LP5521 I²C address is pin selectable from four different choices. If 8-bit address is used for programming, the 8th bit is 1 for read and 0 for write. Table 9 shows the 8-bit I²C addresses.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device sends an acknowledge signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a start condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

Figure 22. I²C Chip Address

7.5.1.6 Control Register Write Cycle

• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master will send further data bytes the control register address is incremented by one after acknowledge signal.
• Write cycle ends when the master creates stop condition.

7.5.1.7 Control Register Read Cycle

• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address is incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition.

<>Data from master [ ] Data from slave

Figure 23. Register Write Format

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in Figure 24.

w = write (SDA = 0)
r = read (SDA = 1)
ack = acknowledge (SDA pulled down by either master or slave
rs = repeated start
id = 7-bit chip address

Figure 24. Register Read Format

Operation modes are defined in register address 01H. Each output channel (R, G, B) operation mode can be configured separately. MODE registers are synchronized to a 32-kHz clock. Delay between consecutive I²C writes to OP_MODE register (01H) need to be longer than 153 µs (typical).

7.5.2.1 Disabled

Each channel can be configured to disabled mode. LED output current is 0 during this mode. Disabled mode resets PC of respective channel.

7.5.2.2 LOAD Program

LP5521 can store 16 commands for each channel (R, G, B). Each command consists of 16 bits. Because one register has only 8 bits, one command requires two I²C register addresses. In order to reduce program load time LP5521 supports address auto incrementation. Register address is incremented after each 8 data bits. Whole program memory can be written in one I²C write sequence.

Program memory is defined in the LP5521 register table, 10H to 2FH for R channel, 30H to 4FH for G channel and 50H to 6FH for B channel. In order to be able to access program memory at least one channel operation mode needs to be LOAD Program.

Memory writes are allowed only to the channel in LOAD mode. All channels are in hold while one or several channels are in LOAD program mode, and PWM values are frozen for the channels which are not in LOAD mode. Program execution continues when all channels are out of LOAD program mode. LOAD Program mode resets PC of respective channel.

7.5.2.3 RUN Program

RUN Program mode executes the commands defined in program memory for respective channel (R, G, B). Execution register bits in ENABLE register define how program is executed. Program start position can be programmed to Program Counter register (see the following tables). By manually selecting the PC start value, user can write different lighting sequences to the memory, and select appropriate sequence with the PC register. If program counter runs to end (15) the next command will be executed from program location 0.

If internal clock is used in the RUN program mode, operation mode needs to be written disabled (00b) before disabling the chip (with CHIP_EN bit or EN pin) to ensure that the sequence starts from the correct program counter (PC) value when restarting the sequence.

PC registers are synchronized to 32 kHz clock. Delay between consecutive I²C writes to PC registers (09H, 0AH, 0BH) need to be longer than 153 µs (typ.).

Note that entering LOAD program or Direct Control Mode from RUN PROGRAM mode is not allowed. Engine execution mode should be set to Hold, and Operation Mode to disabled, when changing operation mode from RUN mode.

EXEC registers are synchronized to 32-kHz clock. Delay between consecutive I²C writes to ENABLE register (00H) need to be longer than 488 μs (typ.).

Table 14. LED Controller Programming Commands

7.5.3.1 RAMP/WAIT

Ramp command generates a PWM ramp starting from current value. At each ramp step the output is incremented by one. Time for one step is defined with Prescale and Step time bits. Minimum time for one step is 0.49 ms and maximum time is 63 × 15.6 ms = 1 second/step, so it is possible to program very fast and also very slow ramps. Increment value defines how many steps are taken in one command. Number of actual steps is Increment + 1. Maximum value is 127d, which corresponds to half of full scale (128 steps). If during ramp command PWM reaches minimum/maximum (0/255) ramp command is executed to the end, and PWM stays at minimum/maximum. This enables ramp command to be used as combined ramp and wait command in a single instruction.

Ramp command can be used as wait instruction when increment is zero.

Setting register 00H bit LOG_EN sets the scale from linear to logarithmic. When LOG_EN = 0 linear scale is used, and when LOG_EN = 1 logarithmic scale is used. By using logarithmic scale the visual effect of the ramp command seems linear to the eye.

Application example:

For example if following parameters are used for ramp:

• Prescale = 1 → cycle time = 15.6 ms
• Step time = 2 → time = 15.6 ms x 2 = 31.2 ms
• Sign = 0 → rising ramp
• Increment = 4 → 5 cycles

Ramp command will be: 0100 0010 0000 0100b = 4204H

If current PWM value is 3, and the first command is as described above and next command is a ramp with otherwise same parameters, but with Sign = 1 (Command = 4284H), the result will be like in Figure 25:

Figure 25. Example of 2 Sequential Ramp Commands.

7.5.3.2 Set PWM

Set PWM output value from 0 to 255. Command takes sixteen 32 kHz clock cycles (= 488 μs). Setting register 00H bit LOG_EN sets the scale from linear to logarithmic.

7.5.3.3 Go to Start

Go to start command resets Program Counter register and continues executing program from the 00H location. Command takes sixteen 32 kHz clock cycles. Note that default value for all program memory registers is 0000H, which is Go to start command.

7.5.3.4 Branch

When branch command is executed, the 'step number' value is loaded to PC and program execution continues from this location. Looping is done by the number defined in loop count parameter. Nested looping is supported (loop inside loop). The number of nested loops is not limited. Command takes sixteen 32-kHz clock cycles.

7.5.3.5 End

End program execution, resets the program counter and sets the corresponding EXEC register to 00b (hold). Command takes sixteen 32-kHz clock cycles.

X means do not care whether 1 or 0.

7.5.3.6 Trigger

Wait or send triggers can be used to, for example, synchronize operation between different channels. Send trigger command takes sixteen 32-kHz clock cycles, and wait for trigger takes at least sixteen 32 kHz clock cycles. The receiving channel stores sent triggers. Received triggers are cleared by wait for trigger command if received triggers match to channels defined in the command. Channel waits for until all defined triggers have been received.

External trigger input signal must be at least two 32-kHz clock cycles (= 61 μs typical) long to be recognized. Trigger output signal is three 32-kHz clock cycles (92 μs typical) long. External trigger signal is active low; that is, when trigger is sent/received the pin is pulled to GND. Sent external trigger is masked; that is, the device which has sent the trigger does not recognize it. If send and wait external trigger are used on the same command, the send external trigger is executed first, then the wait external trigger.

X means do not care whether 1 or 0.

Table 21. Enable Register

Table 22. OP Mode Register

Table 23. R PWM Register

Table 24. G PWM Register

Table 25. B PWM Register

Table 26. R CURRENT Register

Table 27. G CURRENT Register

Table 28. B CURRENT Register

Table 29. CONFIG Register

Table 30. R Channel PC Register

Table 31. G Channel PC Register

Table 32. B Channel PC Register

Table 33. STATUS/INTERRUPT Register

Table 34. RESET Register

Table 35. GPO Register