SNVSCC4A October   2023  – September 2024 LP5811

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Synchronous Boost Converter
        1. 6.3.1.1 Undervoltage Lockout
        2. 6.3.1.2 Enable and Soft Start
        3. 6.3.1.3 Switching Frequency
        4. 6.3.1.4 Current Limit Operation
        5. 6.3.1.5 Boost PWM Mode
        6. 6.3.1.6 Boost PFM Mode
      2. 6.3.2 Analog Dimming
      3. 6.3.3 PWM Dimming
      4. 6.3.4 Autonomous Animation Engine Control
        1. 6.3.4.1 Animation Engine Pattern
        2. 6.3.4.2 Sloper
        3. 6.3.4.3 Animation Engine Unit (AEU)
        4. 6.3.4.4 Animation Pause Unit (APU)
      5. 6.3.5 Protections and Diagnostics
        1. 6.3.5.1 Overvoltage Protection
        2. 6.3.5.2 Output Short-to-Ground Protection
        3. 6.3.5.3 LED Open Detections
        4. 6.3.5.4 LED Short Detections
        5. 6.3.5.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Parameters
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Inductor Selection
        2. 7.2.3.2 Output Capacitor Selection
        3. 7.2.3.3 Input Capacitor Selection
        4. 7.2.3.4 Program Procedure
        5. 7.2.3.5 Programming Example
      4. 7.2.4 Application Performance Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Programming

The LP5811 is compatible with I2C standard specification. The device supports standard mode (100-kHz maximum), fast mode (400-kHz maximum), and fast plus mode (1-MHz maximum). The device has 4 different chip address versions, which allows connecting up to four parallel devices in one I2C bus.

I2C Data Transactions

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when clock signal is LOW. START and STOP conditions classify the beginning and the end of the data transfer session. A START condition is defined as the SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus leader always generates START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP condition. During data transmission, the bus leader can generate repeated START conditions. First START and repeated START conditions are functionally equivalent.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the leader. The leader releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the leader is the receiver, the receiver must indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out of the follower. This negative acknowledge still includes the acknowledge clock pulse (generated by the leader), but the SDA line is not pulled down.

I2C Data Format

The address and data bits are transmitted MSB first with 8-bits length format in each cycle. Each transmission is started with Address Byte 1, which are divided into 5 bits of the chip address, 2 higher bits of the register address, and 1 read/write bit. The other 8 lower bits of register address are put in Address Byte 2.The device supports both independent mode and broadcast mode. The auto-increment feature allows writing / reading several consecutive registers within one transmission. If not consecutive, a new transmission must be started. The Bit 4 and Bit 3 are determined by the device, which can refer to Section 4.

Table 6-4 I2C Data Format
Address Byte1 Chip Address Register Address R/W
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Independent 1 0 1 Bit 4 Bit 3 9th bit 8th bit R: 1 W: 0
Broadcast 1 1 0 1 1
Address Byte2 Register Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
7th bit 6th bit 5th bit 4th bit 3rd bit 2nd bit 1st bit 0 bit
LP5811 I2C Write Timming Figure 6-11 I2C Write Timming
LP5811 I2C Read Timing Figure 6-12 I2C Read Timing