SNVSCC4A October 2023 – September 2024 LP5811
PRODUCTION DATA
The output capacitor is selected to meet the requirements of output ripple and loop stability. The ripple voltage is related to capacitor capacitance and equivalent series resistance (ESR). Assuming a ceramic capacitor with zero ESR, the minimum capacitance for a given ripple voltage can be calculated by Equation 9.
where
The ESR impact on the output ripple must be considered if tantalum or aluminum electrolytic capacitors are used. The output peak-to-peak ripple voltage caused by the ESR of the output capacitors can be calculated by Equation 10.
The derating of a ceramic capacitor under dc bias voltage, aging, and ac signal need to be considered during design. For example, the dc bias voltage can significantly reduce capacitance. A ceramic capacitor can lose more than 50% of capacitance at the rated voltage. Therefore, enough the voltage rating margin must be left to get adequate capacitance at the required output voltage. Increasing the output capacitor can make the output ripple voltage smaller in PWM mode.
TI recommends using the X5R or X7R ceramic output capacitor in the range of 4μF to 1000μF effective capacitance. 10μF effective capacitance is recommended in typical application, which means around 22μF rated capacitance. If the output capacitor is below the range, the boost regulator can potentially become unstable.