SNVSCC9B November   2023  – December 2024 LP5812

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Time-Cross-Multiplexing (TCM) Scheme
        1. 7.3.1.1 Direct drive mode
        2. 7.3.1.2 TCM Drive Mode
        3. 7.3.1.3 Mix drive mode
        4. 7.3.1.4 Ghosting Elimination
      2. 7.3.2 Analog Dimming
      3. 7.3.3 PWM Dimming
      4. 7.3.4 Autonomous Animation Engine Control
        1. 7.3.4.1 Animation Engine Pattern
        2. 7.3.4.2 Sloper
        3. 7.3.4.3 Animation Engine Unit (AEU)
        4. 7.3.4.4 Animation Pause Unit (APU)
      5. 7.3.5 Protections and Diagnostics
        1. 7.3.5.1 LED Open Detections
        2. 7.3.5.2 LED Short Detections
        3. 7.3.5.3 Thermal Shutdown
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Parameters
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Capacitor Selection
        2. 8.2.3.2 Program Procedure
        3. 8.2.3.3 Programming Example
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBH|9
  • DSD|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

Unless specified otherwise, typical characteristics apply over the full ambient temperature range (–40°C < TA < +85°C ), VIN = 3.6 V, VCC = 5 V, CIN = 1 μF, COUT = 1 μF.
I2C Timing Requirements MIN NOM MAX UNIT
Standard-mode
fSCL SCL clock frequency 0 100 kHz
tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 µs
tLOW LOW period of the SCL clock 4.7 µs
tHIGH HIGH period of the SCL clock 4 µs
tSU_STA Set-up time for a repeated START condition 4.7 µs
tHD_DAT Data hold time 0 µs
tSU_DAT Data set-up time 250 ns
tr Rise time of both SDA and SCL signals 1000 ns
tf Fall time of both SDA and SCL signals 300 ns
tSU_STO Set-up time for STOP condition 4 µs
tBUF Bus free time between a STOP and START condition 4.7 µs
Cb Capacitive load for each bus line 400 pF
Fast-mode
fSCL SCL clock frequency 0 400 kHz
tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.6 µs
tLOW LOW period of the SCL clock 1.3 µs
tHIGH HIGH period of the SCL clock 0.6 µs
tSU_STA Set-up time for a repeated START condition 0.6 µs
tHD_DAT Data hold time 0 µs
tSU_DAT Data set-up time 100 ns
tr Rise time of both SDA and SCL signals 300 ns
tf Fall time of both SDA and SCL signals 300 ns
tSU_STO Set-up time for STOP condition 0.6 µs
tBUF Bus free time between a STOP and START condition 1.3 µs
Cb Capacitive load for each bus line 400 pF
Fast-mode Plus
fSCL SCL clock frequency 0 1000 kHz
tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.26 µs
tLOW LOW period of the SCL clock 0.5 µs
tHIGH HIGH period of the SCL clock 0.26 µs
tSU_STA Set-up time for a repeated START condition 0.26 µs
tHD_DAT Data hold time 0 µs
tSU_DAT Data set-up time 50 ns
tr Rise time of both SDA and SCL signals 120 ns
tf Fall time of both SDA and SCL signals 120 ns
tSU_STO Set-up time for STOP condition 0.26 µs
tBUF Bus free time between a STOP and START condition 0.5 µs
Cb Capacitive load for each bus line 550 pF
Misc. Timing Requirements
fCLK_EX VSYNC input clock frequency 6 MHz