SNVSBU8A May   2021  – November 2021 LP5860

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Time-Multiplexing Matrix
      2. 8.3.2 Analog Dimming (Current Gain Control)
      3. 8.3.3 PWM Dimming
      4. 8.3.4 ON and OFF Control
      5. 8.3.5 Data Refresh Mode
      6. 8.3.6 Full Addressable SRAM
      7. 8.3.7 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Program Procedure
      5. 9.2.5 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1 Layout Guidelines

Below guidelines for layout design can help to get a better on-board performance.

  • The decoupling capacitors CVCC and CVLED for power supply must be close to the chip to have minimized the impact of high-frequency noise and ripple from power. CVCAP for internal LDO must be put as close to chip as possible. GND plane connections to CVLED and GND pins must be on TOP layer copper with multiple vias connecting to system ground plane. CVIO for internal enable block also must be put as close to chip as possible.
  • The exposed thermal pad must be well soldered to the board, which can have better mechanical reliability. This action can optimize heat transfer so that increasing thermal performance. The AGND pin must be connected to thermal pad and system ground.
  • The major heat flow path from the package to the ambient is through copper on the PCB. Several methods can help thermal performance. Below exposed thermal pad of IC, putting much vias through the PCB to other ground layer can dissipate more heat. Maximizing the copper coverage on the PCB can increase the thermal conductivity of the board.
  • Low inductive and resistive path of switch load loop can help to provide a high slew rate. Therefore, path of VLED – SWx must be short and wide and avoid parallel wiring and narrow trace. Transient current in SWx pins is much larger than CSy pins, so that trace for SWx must be wider than CSy.