SNVSC54 January   2022 LP5861

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Dimming (Current Gain Control)
      2. 8.3.2 PWM Dimming
      3. 8.3.3 ON and OFF Control
      4. 8.3.4 Data Refresh Mode
      5. 8.3.5 Full Addressable SRAM
      6. 8.3.6 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CONFIG Registers
      2. 8.6.2 GROUP Registers
      3. 8.6.3 DOTGROUP Registers
      4. 8.6.4 DOTONOFF Registers
      5. 8.6.5 FAULT Registers
      6. 8.6.6 RESET Registers
      7. 8.6.7 DC Registers
      8. 8.6.8 PWM Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Program Procedure
      5. 9.2.5 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Figure 6-1 LP5861 RSM Package 32-Pin VQFN with Exposed Thermal Pad Top View
Table 6-1 Pin Functions
PINI/ODESCRIPTION
NO.NAME
1 VCC Power Power supply for device. A 1-μF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
2CS0OCurrent sink 0. If not used, this pin must be left floating.
3CS1OCurrent sink 1. If not used, this pin must be left floating.
4CS2OCurrent sink 2. If not used, this pin must be left floating.
5CS3OCurrent sink 3. If not used, this pin must be left floating.
6CS4OCurrent sink 4. If not used, this pin must be left floating.
7CS5OCurrent sink 5. If not used, this pin must be left floating.
8CS6OCurrent sink 6. If not used, this pin must be left floating.
9CS7OCurrent sink 7. If not used, this pin must be left floating.
10CS8OCurrent sink 8. If not used, this pin must be left floating.
11/12/13/14SW0OHigh-side PMOS switch output. All four pinsmust be tied together. If not used, this pin must be left floating.
15VLEDPowerPower input for high-side switches.
16CS9OCurrent sink 9. If not used, this pin must be left floating.
17CS10OCurrent sink 10. If not used, this pin must be left floating.
18CS11OCurrent sink 11. If not used, this pin must be left floating.
19CS12OCurrent sink 12. If not used, this pin must be left floating.
20CS13OCurrent sink 13. If not used, this pin must be left floating.
21CS14OCurrent sink 14. If not used, this pin must be left floating.
22CS15OCurrent sink 15. If not used, this pin must be left floating.
23CS16OCurrent sink 16. If not used, this pin must be left floating.
24CS17OCurrent sink 17. If not used, this pin must be left floating.
25VCAPOInternal LDO output. A 1-μF capacitor must be connected between this pin with GND. Place the capacitor as close to the device as possible.
26IFSIInterface type select. I2C is selected when IFS is low. SPI is selected when IFS is high. A resistor must be connected between VIO and this pin.
27VSYNCIExternal synchronize signal for display mode 2 and mode 3.
28SCL_SCLKII2C clock input or SPI clock input. Pull up to VIO when configured as I2C.
29SDA_MOSII/OI2C data input or SPI leader output follower input. Pull up to VIO when configured as I2C.
30ADDR0_MISOI/OI2C address select 0 or SPI leader input follower output
31ADDR1_SSII2C address select 1 or SPI follower select
32VIO_ENPower,IPower supply for digital circuits and chip enable. A 1-nF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
Exposed Thermal PadGNDGroundCommon ground plane