SNVSCE4A may   2023  – august 2023 LP5861T

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7.     15
    8. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Dimming (Current Gain Control)
      2. 8.3.2 PWM Dimming
      3. 8.3.3 ON and OFF Control
      4. 8.3.4 Data Refresh Mode
      5. 8.3.5 Full Addressable SRAM
      6. 8.3.6 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CONFIG Registers
      2. 8.6.2 GROUP Registers
      3. 8.6.3 DOTGROUP Registers
      4. 8.6.4 DOTONOFF Registers
      5. 8.6.5 FAULT Registers
      6. 8.6.6 RESET Registers
      7. 8.6.7 DC Registers
      8. 8.6.8 PWM Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Program Procedure
      4. 9.2.4 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.2 GROUP Registers

Table 8-15 lists the GROUP registers. All register offset addresses not listed in Table 8-15 must be considered as reserved locations and the register contents must not be modified.

Table 8-15 GROUP Registers
AddressAcronymRegister NameSection
5hMaster_briGlobal PWM configurationGo
6hGroup0_briGroup1 PWM configurationGo
7hGroup1_briGroup2 PWM configurationGo
8hGroup2_briGroup3 PWM configurationGo
9hR_current_setGroup1 current configurationGo
AhG_current_setGroup2 current configurationGo
BhB_current_setGroup3 current configurationGo

8.6.2.1 Master_bri Register (Address = 5h) [Default = FFh]

Master_bri is shown in Figure 8-22 and described in Table 8-16.

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Figure 8-22 Master_bri Register
76543210
PWM_Global
R/W-FFh
Table 8-16 Master_bri Register Field Descriptions
BitFieldTypeDefaultDescription
7-0PWM_GlobalR/WFFh Global PWM setting

8.6.2.2 Group0_bri Register (Address = 6h) [Default = FFh]

Group0_bri is shown in Figure 8-23 and described in Table 8-17.

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Figure 8-23 Group0_bri Register
76543210
PWM_Group1
R/W-FFh
Table 8-17 Group0_bri Register Field Descriptions
BitFieldTypeDefaultDescription
7-0PWM_Group1R/WFFh Group1 PWM setting

8.6.2.3 Group1_bri Register (Address = 7h) [Default = FFh]

Group1_bri is shown in Figure 8-24 and described in Table 8-18.

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Figure 8-24 Group1_bri Register
76543210
PWM_Group2
R/W-FFh
Table 8-18 Group1_bri Register Field Descriptions
BitFieldTypeDefaultDescription
7-0PWM_Group2R/WFFh Group2 PWM setting

8.6.2.4 Group2_bri Register (Address = 8h) [Default = FFh]

Group2_bri is shown in Figure 8-25 and described in Table 8-19.

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Figure 8-25 Group2_bri Register
76543210
PWM_Group3
R/W-FFh
Table 8-19 Group2_bri Register Field Descriptions
BitFieldTypeDefaultDescription
7-0PWM_Group3R/WFFh Group3 PWM setting

8.6.2.5 R_current_set Register (Address = 9h) [Default = 40h]

R_current_set is shown in Figure 8-26 and described in Table 8-20.

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Figure 8-26 R_current_set Register
76543210
RESERVEDCC_Group1
R-0hR/W-40h
Table 8-20 R_current_set Register Field Descriptions
BitFieldTypeDefaultDescription
7RESERVEDR0h Reserved
6-0CC_Group1R/W40h Color-group current setting (CC) of group 1 (CS0, CS3, CS6, CS9, CS12, CS15)

8.6.2.6 G_current_set Register (Address = Ah) [Default = 40h]

G_current_set is shown in Figure 8-27 and described in Table 8-21.

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Figure 8-27 G_current_set Register
76543210
RESERVEDCC_Group2
R-0hR/W-40h
Table 8-21 G_current_set Register Field Descriptions
BitFieldTypeDefaultDescription
7RESERVEDR0h Reserved
6-0CC_Group2R/W40h Color-group current setting (CC) of group 2 (CS1, CS4, CS7, CS10, CS13, CS16)

8.6.2.7 B_current_set Register (Address = Bh) [Default = 40h]

B_current_set is shown in Figure 8-28 and described in Table 8-22.

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Figure 8-28 B_current_set Register
76543210
RESERVEDCC_Group3
R-0hR/W-40h
Table 8-22 B_current_set Register Field Descriptions
BitFieldTypeDefaultDescription
7RESERVEDR0h Reserved
6-0CC_Group3R/W40h Color-group current setting (CC) of group 3 (CS2, CS5, CS8, CS11, CS14, CS17)