SNVSCE4A may   2023  – august 2023 LP5861T

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7.     15
    8. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Dimming (Current Gain Control)
      2. 8.3.2 PWM Dimming
      3. 8.3.3 ON and OFF Control
      4. 8.3.4 Data Refresh Mode
      5. 8.3.5 Full Addressable SRAM
      6. 8.3.6 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CONFIG Registers
      2. 8.6.2 GROUP Registers
      3. 8.6.3 DOTGROUP Registers
      4. 8.6.4 DOTONOFF Registers
      5. 8.6.5 FAULT Registers
      6. 8.6.6 RESET Registers
      7. 8.6.7 DC Registers
      8. 8.6.8 PWM Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Program Procedure
      4. 9.2.4 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.6 RESET Registers

Table 8-41 lists the RESET registers, including LOD_CLR registers, LSD_CLR registers and Reset registers. All register offset addresses not listed in Table 8-41 must be considered as reserved locations and the register contents must not be modified.

Table 8-41 RESET Registers
AddressAcronymRegister NameSection
A7hLOD_clearLOD flag clear registerGo
A8hLSD_clearLSD flag clear registerGo
A9hResetSoftware reset registerGo

8.6.6.1 LOD_clear Register (Address = A7h) [Default = 0h]

LOD_clear is shown in Figure 8-44 and described in Table 8-42.

Return to the Summary Table.

Figure 8-44 LOD_clear Register
76543210
RESERVEDLOD_Clear
R-0hW-0h
Table 8-42 LOD_clear Register Field Descriptions
BitFieldTypeDefaultDescription
7-4RESERVEDR0h Reserved
3-0LOD_ClearW0h Write Fh to clear all LOD indication bits

8.6.6.2 LSD_clear Register (Address = A8h) [Default = 0h]

LSD_clear is shown in Figure 8-45 and described in Table 8-43.

Return to the Summary Table.

Figure 8-45 LSD_clear Register
76543210
RESERVEDLSD_Clear
R-0hW-0h
Table 8-43 LSD_clear Register Field Descriptions
BitFieldTypeDefaultDescription
7-4RESERVEDR0h Reserved
3-0LSD_ClearW0h Write Fh to clear all LSD indication bits

8.6.6.3 Reset Register (Address = A9h) [Default = 0h]

Reset is shown in Figure 8-46 and described in Table 8-44.

Return to the Summary Table.

Figure 8-46 Reset Register
76543210
Reset
W-0h
Table 8-44 Reset Register Field Descriptions
BitFieldTypeDefaultDescription
7-0ResetW0h Write FFh to reset the device