SNVSCE4A may   2023  – august 2023 LP5861T

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7.     15
    8. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Dimming (Current Gain Control)
      2. 8.3.2 PWM Dimming
      3. 8.3.3 ON and OFF Control
      4. 8.3.4 Data Refresh Mode
      5. 8.3.5 Full Addressable SRAM
      6. 8.3.6 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CONFIG Registers
      2. 8.6.2 GROUP Registers
      3. 8.6.3 DOTGROUP Registers
      4. 8.6.4 DOTONOFF Registers
      5. 8.6.5 FAULT Registers
      6. 8.6.6 RESET Registers
      7. 8.6.7 DC Registers
      8. 8.6.8 PWM Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Program Procedure
      4. 9.2.4 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1 CONFIG Registers

Table 8-9 lists the CONFIG registers. All register offset addresses not listed in Table 8-9 must be considered as reserved locations and the register contents must not be modified.

Table 8-9 CONFIG Registers
AddressAcronymRegister NameSection
0hChip_enChip enableGo
1hDev_initialDevice initializationGo
2hDev_config1Device configuration register 1Go
3hDev_config2Device configuration register 2Go
4hDev_config3Device configuration register 3Go

8.6.1.1 Chip_en Register (Address = 0h) [Default = 0h]

Chip_en is shown in Figure 8-17 and described in Table 8-10.

Return to the Summary table.

Figure 8-17 Chip_en Register
76543210
RESERVEDChip_EN
R-0hR/W-0h
Table 8-10 Chip_en Register Field Descriptions
BitFieldTypeDefaultDescription
7-1RESERVEDR0h Reserved
0Chip_ENR/W0h Chip enable
0h = Disabled
1h = Enabled

8.6.1.2 Dev_initial Register (Address = 1h) [Default = 5Eh]

Dev_initial is shown in Figure 8-18 and described in Table 8-11.

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Figure 8-18 Dev_initial Register
76543210
RESERVEDData_Ref_ModePWM_Fre
R-BhR/W-3hR/W-0h
Table 8-11 Dev_initial Register Field Descriptions
BitFieldTypeDefaultDescription
7-3RESERVEDRBh Reserved
2-1Data_Ref_ModeR/W3h Data refresh mode slection
0h = Mode 1
1h = Mode 2
2h = Mode 3
3h = Mode 3
0PWM_FreR/W0h Output PWM frequency setting
0h = 125kHz
1h = 62.5kHz

8.6.1.3 Dev_config1 Register (Address = 2h) [Default = 0h]

Dev_config1 is shown in Figure 8-19 and described in Table 8-12.

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Figure 8-19 Dev_config1 Register
76543210
RESERVEDPWM_Scale_ModePWM_Phase_ShiftRESERVED
R-0hR/W-0hR/W-0hR-0h
Table 8-12 Dev_config1 Register Field Descriptions
BitFieldTypeDefaultDescription
7-3RESERVEDR0h Reserved
2PWM_Scale_ModeR/W0h Dimming scale setting of final PWM generator
0h = Linear scale dimming curve
1h = Exponential scale dimming curve
1PWM_Phase_ShiftR/W0h PWM phase shift selection
0h = Phase shift off
1h = Phase shift on
0RESERVEDR0hReserved

8.6.1.4 Dev_config2 Register (Address = 3h) [Default = 0h]

Dev_config2 is shown in Figure 8-20 and described in Table 8-13.

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Figure 8-20 Dev_config2 Register
76543210
Comp_Group3Comp_Group2Comp_Group1RESERVED
R/W-0hR/W-0hR/W-0hR-0h
Table 8-13 Dev_config2 Register Field Descriptions
BitFieldTypeDefaultDescription
7-6Comp_Group3R/W0h Low brightness compensation clock shift number setting for group1
0h = off
1h = 1 clock
2h = 2 clock
3h = 3 clock
5-4Comp_Group2R/W0h Low brightness compensation clock shift number setting for group2
0h = off
1h = 1 clock
2h = 2 clock
3h = 3 clock
3-2Comp_Group1R/W0h Low brightness compensation clock shift number setting for group3
0h = off
1h = 1 clock
2h = 2 clock
3h = 3 clock
1-0RESERVEDR0hReserved

8.6.1.5 Dev_config3 Register (Address = 4h) [Default = 57h]

Dev_config3 is shown in Figure 8-21 and described in Table 8-14.

Return to the Summary table.

Figure 8-21 Dev_config3 Register
76543210
RESERVEDMaximum_CurrentRESERVED
R-5hR/W-3hR-1h
Table 8-14 Dev_config3 Register Field Descriptions
BitFieldTypeDefaultDescription
7-4RESERVEDR5hReserved
3-1Maximum_CurrentR/W3h Maximum current cetting (MC)
0h = 7.5 mA
1h = 12.5 mA
2h = 25 mA
3h = 37.5 mA (Default)
4h = 50 mA
5h = 75 mA
6h = 100 mA
7h = 125 mA
0RESERVEDR1hReserved