SNVSCE4A may   2023  – august 2023 LP5861T

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7.     15
    8. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Dimming (Current Gain Control)
      2. 8.3.2 PWM Dimming
      3. 8.3.3 ON and OFF Control
      4. 8.3.4 Data Refresh Mode
      5. 8.3.5 Full Addressable SRAM
      6. 8.3.6 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CONFIG Registers
      2. 8.6.2 GROUP Registers
      3. 8.6.3 DOTGROUP Registers
      4. 8.6.4 DOTONOFF Registers
      5. 8.6.5 FAULT Registers
      6. 8.6.6 RESET Registers
      7. 8.6.7 DC Registers
      8. 8.6.8 PWM Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Program Procedure
      4. 9.2.4 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.5 FAULT Registers

Table 8-33 lists the FAULT registers, including Fault_state registers, LOD registers and LSD registers. All register offset addresses not listed in Table 8-33 must be considered as reserved locations and the register contents must not be modified.

Table 8-33 FAULT Registers
AddressAcronymRegister NameSection
64hFault_stateGlobal LOD/LSD indication registerGo
65hDot_lod0LED dot LOD indication register 0Go
66hDot_lod1LED dot LOD indication register 1Go
67hDot_lod2LED dot LOD indication register 2Go
86hDot_lsd0LED dot LSD indication register 0Go
87hDot_lsd1LED dot LSD indication register 1Go
88hDot_lsd2LED dot LSD indication register 2Go

8.6.5.1 Fault_state Register (Address = 64h) [Default = 0h]

Fault_state is shown in Figure 8-37 and described in Table 8-34.

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Figure 8-37 Fault_state Register
76543210
RESERVEDGlobal_LODGlobal_LSD
R-0hR-0hR-0h
Table 8-34 Fault_state Register Field Descriptions
BitFieldTypeDefaultDescription
7-2RESERVEDR0h Reserved
1Global_LODR0h LOD indication bit if there is open fault detected at any LED dot
0h = Not open
1h = Open
0Global_LSDR0h LSD indication bit if there is short fault detected at any LED dot
0h = Not short
1h = Short

8.6.5.2 Dot_lod0 Register (Address = 65h) [Default = 0h]

Dot_lod0 is shown in Figure 8-38 and described in Table 8-35.

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Figure 8-38 Dot_lod0 Register
76543210
CS7_LOD_stateCS6_LOD_stateCS5_LOD_stateCS4_LOD_stateCS3_LOD_stateCS2_LOD_stateCS1_LOD_stateCS0_LOD_state
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-35 Dot_lod0 Register Field Descriptions
BitFieldTypeDefaultDescription
7CS7_LOD_stateR0h CS7 LOD state
0h = Not open
1h = Open
6CS6_LOD_stateR0h CS6 LOD state
0h = Not open
1h = Open
5CS5_LOD_stateR0h CS5 LOD state
0h = Not open
1h = Open
4CS4_LOD_stateR0h CS4 LOD state
0h = Not open
1h = Open
3CS3_LOD_stateR0h CS3 LOD state
0h = Not open
1h = Open
2CS2_LOD_stateR0h CS2 LOD state
0h = Not open
1h = Open
1CS1_LOD_stateR0h CS1 LOD state
0h = Not open
1h = Open
0CS0_LOD_stateR0h CS0 LOD state
0h = Not open
1h = Open

8.6.5.3 Dot_lod1 Register (Address = 66h) [Default = 0h]

Dot_lod1 is shown in Figure 8-39 and described in Table 8-36.

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Figure 8-39 Dot_lod1 Register
76543210
CS15_LOD_stateCS14_LOD_stateCS13_LOD_stateCS12_LOD_stateCS11_LOD_stateCS10_LOD_stateCS9_LOD_stateCS8_LOD_state
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-36 Dot_lod1 Register Field Descriptions
BitFieldTypeDefaultDescription
7CS15_LOD_stateR0h CS15 LOD state
0h = Not open
1h = Open
6CS14_LOD_stateR0h CS14 LOD state
0h = Not open
1h = Open
5CS13_LOD_stateR0h CS13 LOD state
0h = Not open
1h = Open
4CS12_LOD_stateR0h CS12 LOD state
0h = Not open
1h = Open
3CS11_LOD_stateR0h CS11 LOD state
0h = Not open
1h = Open
2CS10_LOD_stateR0h CS10 LOD state
0h = Not open
1h = Open
1CS9_LOD_stateR0h CS9 LOD state
0h = Not open
1h = Open
0CS8_LOD_stateR0h CS8 LOD state
0h = Not open
1h = Open

8.6.5.4 Dot_lod2 Register (Address = 67h) [Default = 0h]

Dot_lod2 is shown in Figure 8-40 and described in Table 8-37.

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Figure 8-40 Dot_lod2 Register
76543210
RESERVEDCS17_LOD_stateCS16_LOD_state
R-0hR-0hR-0h
Table 8-37 Dot_lod2 Register Field Descriptions
BitFieldTypeDefaultDescription
7-2RESERVEDR0h Reserved
1CS17_LOD_stateR0h CS17 LOD state
0h = Not open
1h = Open
0CS16_LOD_stateR0h CS16 LOD state
0h = Not open
1h = Open

8.6.5.5 Dot_lsd0 Register (Address = 86h) [Default = 0h]

Dot_lsd0 is shown in Figure 8-41 and described in Table 8-38.

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Figure 8-41 Dot_lsd0 Register
76543210
CS7_LSD_stateCS6_LSD_stateCS5_LSD_stateCS4_LSD_stateCS3_LSD_stateCS2_LSD_stateCS1_LSD_stateCS0_LSD_state
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-38 Dot_lsd0 Register Field Descriptions
BitFieldTypeDefaultDescription
7CS7_LSD_stateR0h CS7 LSD state
0h = Not short
1h = Short
6CS6_LSD_stateR0h CS6 LSD state
0h = Not short
1h = Short
5CS5_LSD_stateR0h CS5 LSD state
0h = Not short
1h = Short
4CS4_LSD_stateR0h CS4 LSD state
0h = Not short
1h = Short
3CS3_LSD_stateR0h CS3 LSD state
0h = Not short
1h = Short
2CS2_LSD_stateR0h CS2 LSD state
0h = Not short
1h = Short
1CS1_LSD_stateR0h CS1 LSD state
0h = Not short
1h = Short
0CS0_LSD_stateR0h CS0 LSD state
0h = Not short
1h = Short

8.6.5.6 Dot_lsd1 Register (Address = 87h) [Default = 0h]

Dot_lsd1 is shown in Figure 8-42 and described in Table 8-39.

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Figure 8-42 Dot_lsd1 Register
76543210
CS15_LSD_stateCS14_LSD_stateCS13_LSD_stateCS12_LSD_stateCS11_LSD_stateCS10_LSD_stateCS9_LSD_stateCS8_LSD_state
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-39 Dot_lsd1 Register Field Descriptions
BitFieldTypeDefaultDescription
7CS15_LSD_stateR0h CS15 LSD state
0h = Not short
1h = Short
6CS14_LSD_stateR0h CS14 LSD state
0h = Not short
1h = Short
5CS13_LSD_stateR0h CS13 LSD state
0h = Not short
1h = Short
4CS12_LSD_stateR0h CS12 LSD state
0h = Not short
1h = Short
3CS11_LSD_stateR0h CS11 LSD state
0h = Not short
1h = Short
2CS10_LSD_stateR0h CS10 LSD state
0h = Not short
1h = Short
1CS9_LSD_stateR0h CS9 LSD state
0h = Not short
1h = Short
0CS8_LSD_stateR0h CS8 LSD state
0h = Not short
1h = Short

8.6.5.7 Dot_lsd2 Register (Address = 88h) [Default = 0h]

Dot_lsd2 is shown in Figure 8-43 and described in Table 8-40.

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Figure 8-43 Dot_lsd2 Register
76543210
RESERVEDCS17_LSD_stateCS16_LSD_state
R-0hR-0hR-0h
Table 8-40 Dot_lsd2 Register Field Descriptions
BitFieldTypeDefaultDescription
7-2RESERVEDR0h Reserved
1CS17_LSD_stateR0h CS17 LSD state
0h = Not short
1h = Short
0CS16_LSD_stateR0h CS16 LSD state
0h = Not short
1h = Short