SNVSC53 December   2021 LP5862

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Time-Multiplexing Matrix
      2. 8.3.2 Analog Dimming (Current Gain Control)
      3. 8.3.3 PWM Dimming
      4. 8.3.4 ON and OFF Control
      5. 8.3.5 Data Refresh Mode
      6. 8.3.6 Full Addressable SRAM
      7. 8.3.7 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Program Procedure
      5. 9.2.5 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Figure 6-1 LP5862 RKP Package 40-Pin VQFN With Exposed Thermal Pad Top View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 VCC Power Power supply for device. A 1-μF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
2 CS0 O Current sink 0. If not used, this pin must be left floating.
3 CS1 O Current sink 1. If not used, this pin must be left floating.
4 CS2 O Current sink 2. If not used, this pin must be left floating.
5 CS3 O Current sink 3. If not used, this pin must be left floating.
6 CS4 O Current sink 4. If not used, this pin must be left floating.
7 CS5 O Current sink 5. If not used, this pin must be left floating.
8 CS6 O Current sink 6. If not used, this pin must be left floating.
9 CS7 O Current sink 7. If not used, this pin must be left floating.
10 CS8 O Current sink 8. If not used, this pin must be left floating.
11/12 SW0 O High-side PMOS switch output 0. Both 2 pins must be tied together. If not used, this pin must be left floating.
13/14 SW1 O High-side PMOS switch output 1. Both 2 pins must be tied together. If not used, this pin must be left floating.
15 VLED Power Power input for high-side switches
16 CS9 O Current sink 9. If not used, this pin must be left floating.
17 CS10 O Current sink 10. If not used, this pin must be left floating.
18 CS11 O Current sink 11. If not used, this pin must be left floating.
19 CS12 O Current sink 12. If not used, this pin must be left floating.
20 CS13 O Current sink 13. If not used, this pin must be left floating.
21 CS14 O Current sink 14. If not used, this pin must be left floating.
22 CS15 O Current sink 15. If not used, this pin must be left floating.
23 CS16 O Current sink 16. If not used, this pin must be left floating.
24 CS17 O Current sink 17. If not used, this pin must be left floating.
25 VCAP O Internal LDO output. An 1-μF capacitor must be connected between this pin with GND. Place the capacitor as close to the device as possible.
26 IFS I Interface type select. I2C is selected when IFS is low. SPI is selected when IFS is high. A resistor must be connected between VIO and this pin.
27 VSYNC I External synchronize signal for display mode 2 and mode 3
28 SCL_SCLK I I2C clock input or SPI clock input. Pull up to VIO when configured as I2C.
29 SDA_MOSI I/O I2C data input or SPI leader output follower input. Pull up to VIO when configured as I2C.
30 ADDR0_MISO I/O I2C address select 0 or SPI leader input follower output
31 ADDR1_SS I I2C address select 1 or SPI follower select
32 VIO_EN Power,I Power supply for digital circuits and chip enable. A 1-nF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
Exposed Thermal Pad GND Ground Common ground plane