SNVSC52 December   2021 LP5864

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Time-Multiplexing Matrix
      2. 8.3.2 Analog Dimming (Current Gain Control)
      3. 8.3.3 PWM Dimming
      4. 8.3.4 ON and OFF Control
      5. 8.3.5 Data Refresh Mode
      6. 8.3.6 Full Addressable SRAM
      7. 8.3.7 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Program Procedure
      5. 9.2.5 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Typical Characteristics

Unless specified otherwise, typical characteristics apply over the full ambient temperature range (–55°C < TA < +125°C for LP5860MRKPR, LP5864MRSMR, and LP5866MDBTR while –40°C < TA < +85°C for the other devices), VCC = 3.3 V, VIO = 3.3 V, VLED = 5 V, ILED_Peak = 50 mA, CVLED = 1 μF, CVCC = 1 μF.

Figure 7-3 VCC UVLO Rising and Falling Thresholds
Figure 7-5 VSAT vs Temperature
Figure 7-7 VSAT vs Current Sinks (30 mA)
TA = 25°C
Figure 7-9 Current Sinks Voltage vs Current
Figure 7-4 VCC UVLO Hysteresis
Figure 7-6 VSAT vs Current Sinks (50 mA)
Figure 7-8 VSAT vs Current Sinks (10 mA)
Figure 7-10 High Side Switch RDSON