SNVSC52
December 2021
LP5864
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Time-Multiplexing Matrix
8.3.2
Analog Dimming (Current Gain Control)
8.3.3
PWM Dimming
8.3.4
ON and OFF Control
8.3.5
Data Refresh Mode
8.3.6
Full Addressable SRAM
8.3.7
Protections and Diagnostics
8.4
Device Functional Modes
8.5
Programming
8.6
Register Maps
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Application
9.2.2
Design Requirements
9.2.3
Detailed Design Procedure
9.2.4
Program Procedure
9.2.5
Application Performance Plots
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Support Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RSM|32
MPQF195B
Thermal pad, mechanical data (Package|Pins)
RSM|32
QFND112H
Orderable Information
snvsc52_oa
snvsc52_pm
7.2
ESD Ratings
VALUE
UNIT
V
(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
±3000
V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins
(2)
±1000
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.