SNVSCE2B May   2023  – November 2023 LP5868T

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7.     14
    8. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Time-Multiplexing Matrix
      2. 7.3.2 Analog Dimming (Current Gain Control)
        1. 7.3.2.1 Global 3-Bits Maximum Current (MC) Setting
        2. 7.3.2.2 3 Groups of 7-Bits Color Current (CC) Setting
        3. 7.3.2.3 Individual 8-bit Dot Current (DC) Setting
      3. 7.3.3 PWM Dimming
        1. 7.3.3.1 Individual 8-Bit / 16-Bit PWM for Each LED Dot
        2. 7.3.3.2 Programmable Groups of 8-Bit PWM Dimming
        3. 7.3.3.3 8-Bit PWM for Global Dimming
      4. 7.3.4 ON and OFF Control
      5. 7.3.5 Data Refresh Mode
      6. 7.3.6 Full Addressable SRAM
      7. 7.3.7 Protections and Diagnostics
        1. 7.3.7.1 LED Open Detection
        2. 7.3.7.2 LED Short Detection
        3. 7.3.7.3 Thermal Shutdown
        4. 7.3.7.4 UVLO (Under Voltage Lock Out)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Interface Selection
      2. 7.5.2 I2C Interface
        1. 7.5.2.1 I2C Data Transactions
        2. 7.5.2.2 I2C Data Format
        3. 7.5.2.3 Multiple Devices Connection
      3. 7.5.3 Programming
        1. 7.5.3.1 SPI Data Transactions
        2. 7.5.3.2 SPI Data Format
        3. 7.5.3.3 Multiple Devices Connection
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Program Procedure
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VDD Input Supply Recommendations
      2. 8.3.2 VLED Input Supply Recommendations
      3. 8.3.3 VIO Input Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

LP5868T LP5868T RKP Package 40-Pin VQFN with Exposed Thermal Pad Top View Figure 5-1 LP5868T RKP Package 40-Pin VQFN with Exposed Thermal Pad Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 CS0 O Current sink 0. If not used, this pin must be floating.
2 CS1 O Current sink 1. If not used, this pin must be floating.
3 CS2 O Current sink 2. If not used, this pin must be floating.
4 CS3 O Current sink 3. If not used, this pin must be floating.
5 CS4 O Current sink 4. If not used, this pin must be floating.
6 CS5 O Current sink 5. If not used, this pin must be floating.
7 CS6 O Current sink 6. If not used, this pin must be floating.
8 CS7 O Current sink 7. If not used, this pin must be floating.
9 CS8 O Current sink 8. If not used, this pin must be floating.
10 SW0 O High-side PMOS switch output for scan line 0. If not used, this pin must be floating.
11 SW1 O High-side PMOS switch output for scan line 1. If not used, this pin must be floating.
12 SW2 O High-side PMOS switch output for scan line 2. If not used, this pin must be floating.
13 SW3 O High-side PMOS switch output for scan line 3. If not used, this pin must be floating.
14 SW4 O High-side PMOS switch output for scan line 4. If not used, this pin must be floating.
15 SW5 O High-side PMOS switch output for scan line 5. If not used, this pin must be floating.
16 VLED Power Power input for high-side switches.
17 SW6 O High-side PMOS switch output for scan line 6. If not used, this pin must be floating.
18 SW7 O High-side PMOS switch output for scan line 7. If not used, this pin must be floating.
19 NC - No connection.
20 NC - No connection.
21 NC - No connection.
22 CS9 O Current sink 9. If not used, this pin must be floating.
23 CS10 O Current sink 10. If not used, this pin must be floating.
24 CS11 O Current sink 11. If not used, this pin must be floating.
25 CS12 O Current sink 12. If not used, this pin must be floating.
26 CS13 O Current sink 13. If not used, this pin must be floating.
27 CS14 O Current sink 14. If not used, this pin must be floating.
28 CS15 O Current sink 15. If not used, this pin must be floating.
29 CS16 O Current sink 16. If not used, this pin must be floating.
30 CS17 O Current sink 17. If not used, this pin must be floating.
31 AGND Ground Analog ground. Must be connected to exposed thermal pad and common ground plane.
32 VCAP O Internal LDO output. An 1μF capacitor must be connected between this pin with GND. Place the capacitor as close to the device as possible.
33 IFS I Interface type select. I2C is selected when IFS is low. SPI is selected when IFS is high. A resistor must be connected between VIO and this pin.
34 VSYNC I External synchronize signal for display mode 2 and mode 3.
35 SCL_SCLK I I2C clock input or SPI clock input. Pull up to VIO when configured as I2C.
36 SDA_MOSI I/O I2C data input or SPI leader output follower input. Pull up to VIO when configured as I2C.
37 ADDR0_MISO I/O I2C address select 0 or SPI leader input follower output.
38 ADDR1_SS I I2C address select 1 or SPI follower select.
39 VIO_EN Power,I Power supply for digital circuits and chip enable. An 1nF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
40 VCC Power Power supply for device. A 1μF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
Exposed Thermal Pad GND Ground Must be connected to AGND and common ground plane.